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71V321S55PFG PDF预览

71V321S55PFG

更新时间: 2024-11-02 00:23:23
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 124K
描述
HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

71V321S55PFG 数据手册

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HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH  
INTERRUPTS  
IDT71V321S/L  
Features  
High-speed access  
On-chip port arbitration logic (IDT71V321 only)  
BUSY output flag  
– Commercial & Industrial: 25/35/55ns (max.)  
Low-power operation  
– IDT71V321S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
– IDT71V321L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Fully asynchronous operation from either port  
Battery backup operation—2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Two INT flags for port-to-port communications  
FunctionalBlockDiagram  
OE  
R
R
OE  
L
CE  
CEL  
R/WR  
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSY  
L
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
(2)  
INTR  
(2)  
L
INT  
3026 drw 01  
NOTES:  
1. IDT71V321(MASTER):BUSYisanoutput  
2. BUSYandINTaretotem-poleoutputs.  
OCTOBER 2015  
1
DSC-3026/12  
©2015 Integrated Device Technology, Inc.  

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