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71V3556 PDF预览

71V3556

更新时间: 2024-11-06 14:57:27
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
29页 332K
描述
3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 3.3V I/O

71V3556 数据手册

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71V3556S  
71V3558S  
71V3556SA  
71V3558SA  
128K x 36, 256K x 18  
3.3V Synchronous ZBT SRAMs  
3.3V I/O, Burst Counter  
Pipelined Outputs  
Features  
4-word burst capability (interleaved or linear)  
128K x 36, 256K x 18 memory configurations  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)  
Optional- Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Supports high performance system speed - 166 MHz (x36)  
(3.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
Positive clock-edge triggered address, data, and control  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
signal registers for fully pipelined applications  
Single R/W (READ/WRITE) control pin  
Functional Block Diagram  
128Kx36 BIT  
MEMORY ARRAY  
LBO  
Address A [0:16]  
D
D
Q
Q
Address  
CE1,CE2, CE2  
R/W  
Control  
CEN  
ADV/LD  
BW/x  
DI  
DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Output Register  
Q
Clock  
Gate  
OE  
5281 drw 01a  
,
TMS  
TDI  
TCK  
Data I/O [0:31],  
I/O P[1:4]  
JTAG  
(SA Version)  
TDO  
TRST  
(optional)  
ZBT®andZeroBusTurnaroundaretrademarksofRenesasandthearchitectureissupportedbyMicronTechnologyandMotorolaInc.  
1
Aug.06.21  

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