Datasheet > 71V2558SA200BGG

71V2558SA200BGG

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	567K
描述
ZBT SRAM, 256KX18, 3.2ns, CMOS, PBGA119, 22 X 14 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119

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71V2558SA200BGG 数据手册

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

SynchronousTruthTable⁽¹⁾

Chip⁽⁵⁾

Enable

ADV/LD

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

CEN

BWx

R/W

(2 cycles later)

(7)

Select

Valid

External

Internal

LOAD WRITE

LOAD READ

(7)

Valid

LOADWRITE /

BURST WRITE

(Advance burst counter)⁽²⁾

(7)

Internal

LOAD READ /

BURST READ

(Advance burst counter)⁽²⁾

Deselect

DESELECT or STOP⁽³⁾

NOOP

HiZ

DESELECT / NOOP

(4)

SUSPEND

Previous Value

4875 tbl 08

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires CE¹= L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

Partial Truth Table for Writes⁽¹⁾

(3)

BW4

OPERATION

R/W

READ

WRITE ALL BYTES

(2)

WRITE BYTE 1 (I/O[0:7], I/OP1

)

WRITE BYTE 2 (I/O[8:15], I/OP2

)

(2,3)

WRITE BYTE 3 (I/O[16:23], I/OP3

)

(2,3)

WRITE BYTE 4 (I/O[24:31], I/OP4

)

NO WRITE

4875 tbl 09

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

6.42

1...6 7 8910 11 12...28

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