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71V2558SA200BGG PDF预览

71V2558SA200BGG

更新时间: 2024-10-29 08:08:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
28页 567K
描述
ZBT SRAM, 256KX18, 3.2ns, CMOS, PBGA119, 22 X 14 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119

71V2558SA200BGG 数据手册

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IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs  
with 2.5V I/O, Burst Counter, and Pipelined Outputs  
Commercial and Industrial Temperature Ranges  
SynchronousTruthTable(1)  
Chip(5)  
Enable  
ADV/LD  
ADDRESS  
USED  
PREVIOUS CYCLE  
CURRENT CYCLE  
I/O  
CEN  
BWx  
R/W  
(2 cycles later)  
(7)  
L
L
L
L
H
X
Select  
Select  
X
L
L
H
Valid  
X
External  
External  
Internal  
X
X
LOAD WRITE  
LOAD READ  
D
(7)  
Q
(7)  
Valid  
LOADWRITE /  
BURST WRITE  
BURST WRITE  
D
(Advance burst counter)(2)  
(7)  
L
X
X
H
X
Internal  
LOAD READ /  
BURST READ  
BURST READ  
Q
(Advance burst counter)(2)  
L
L
H
X
X
X
Deselect  
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)  
NOOP  
HiZ  
HiZ  
X
X
DESELECT / NOOP  
X
(4)  
SUSPEND  
Previous Value  
4875 tbl 08  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of  
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.  
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will  
tri-state two cycles after deselect is initiated.  
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/  
Os remains unchanged.  
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.  
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.  
7. Q - Data read from the device, D - data written to the device.  
Partial Truth Table for Writes(1)  
(3)  
(3)  
BW  
1
BW  
X
L
2
BW  
3
BW4  
OPERATION  
R/W  
H
L
READ  
X
L
X
X
L
WRITE ALL BYTES  
L
H
H
L
(2)  
(2)  
WRITE BYTE 1 (I/O[0:7], I/OP1  
)
L
L
H
L
H
H
H
L
WRITE BYTE 2 (I/O[8:15], I/OP2  
)
L
H
H
H
H
(2,3)  
WRITE BYTE 3 (I/O[16:23], I/OP3  
)
L
H
H
H
(2,3)  
WRITE BYTE 4 (I/O[24:31], I/OP4  
)
L
H
H
NO WRITE  
L
H
4875 tbl 09  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. Multiple bytes may be selected during the same cycle.  
3. N/A for X18 configuration.  
6.42  
9

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