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71V2556XS100PFGI8

更新时间： 2024-11-05 14:29:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 350K
描述
ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100

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71V2556XS100PFGI8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：QFF, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.21
Is Samacsys：N最长访问时间：5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-F100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFF封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.045 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.26 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：FLAT端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

71V2556XS100PFGI8 数据手册

 浏览型号71V2556XS100PFGI8的Datasheet PDF文件第2页浏览型号71V2556XS100PFGI8的Datasheet PDF文件第3页浏览型号71V2556XS100PFGI8的Datasheet PDF文件第4页浏览型号71V2556XS100PFGI8的Datasheet PDF文件第5页浏览型号71V2556XS100PFGI8的Datasheet PDF文件第6页浏览型号71V2556XS100PFGI8的Datasheet PDF文件第7页 
IDT71V2556S/XS  
128K x 36  
IDT71V2556SA/XSA  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread  
or write.  
Features  
◆
128K x 36 memory configurations  
◆
Supports high performance system speed - 166 MHz  
The IDT71V2556 contains data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V2556tobe  
suspended as long as necessary. All synchronous inputs are ignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
(3.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
◆
◆
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis  
initiated.  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
◆
◆
◆
◆
◆
TheIDT71V2556hasanon-chipburstcounter.Intheburstmode,the  
IDT71V2556 can provide four cycles of data for a single address  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
TheIDT71V2556SRAMsutilizeIDT's latesthigh-performanceCMOS  
processandarepackagedinaJEDECstandard14mmx20mm100-pin  
thinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA).  
complaint)  
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP) and 119 ball grid array (BGA)  
Description  
TheIDT71V2556 isa3.3Vhigh-speed4,718,592-bit(4.5Megabit)  
synchronous SRAM. It is designed to eliminate dead bus cycles when  
turning the bus around between reads and writes, or writes and reads.  
Thus, theyhavebeengiventhenameZBTTM, orZeroBusTurnaround.  
PinDescriptionSummary  
A0-A16  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE , CE  
1
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
TMS  
TDI  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
Static  
4875 tbl 01  
APRIL 2011  
1
©2011IntegratedDeviceTechnology,Inc.  
DSC-4875/12  
1234567...23

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