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71V2556SA166BQG8 PDF预览

71V2556SA166BQG8

更新时间： 2024-11-17 08:29:39
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
28页 567K
描述
SRAM

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中文翻译

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71V2556SA166BQG8 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84

71V2556SA166BQG8 数据手册

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128K x 36, 256K x 18  
IDT71V2556S/XS  
IDT71V2558S/XS  
IDT71V2556SA/XSA  
IDT71V2558SA/XSA  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread  
or write.  
The IDT71V2556/58 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V2556/58to  
besuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis  
initiated.  
TheIDT71V2556/58hasanon-chipburstcounter.Intheburstmode,  
theIDT71V2556/58canprovidefourcyclesofdataforasingleaddress  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LDsignal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
◆
128K x 36, 256K x 18 memory configurations  
◆
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
◆
◆
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
◆
◆
◆
◆
◆
complaint)  
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
TheIDT71V2556/58 are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles  
when turning the bus around between reads and writes, or writes and  
TM  
reads. Thus, they have been given the name ZBT , or Zero Bus  
Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
Static  
4875 tbl 01  
MAY 2010  
1
©2010IntegratedDeviceTechnology,Inc.  
DSC-4875/11  
1234567...28

中文翻译

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