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71V12415PHGI8 PDF预览

71V12415PHGI8

更新时间: 2022-02-26 09:57:54
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 68K
描述
3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power and Ground Pinout

71V12415PHGI8 数据手册

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3.3V CMOS Static RAM  
1 Meg (128K x 8-Bit)  
Center Power &  
IDT71V124SA  
Ground Pinout  
Features  
Description  
128K x 8 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise  
TheIDT71V124isa1,048,576-bithigh-speedstaticRAMorganized  
as128Kx8.Itisfabricatedusinghigh-performance,high-reliabilityCMOS  
technology.Thisstate-of-the-arttechnology,combinedwithinnovative  
circuitdesigntechniques,providesacost-effectivesolutionforhigh-speed  
memory needs. The JEDEC center power/GND pinout reduces noise  
generationandimprovessystemperformance.  
Equal access and cycle times  
– Commercial:10/12/15ns  
– Industrial:12/15ns  
One Chip Select plus one Output Enable pin  
Inputs and outputs are LVTTL-compatible  
Single 3.3V supply  
Low power consumption via chip deselect  
Available in a 32-pin 300- and 400-mil Plastic SOJ, and  
32-pin Type II TSOP packages.  
The IDT71V124 has an output enable pin which operates as fast as  
5ns,withaddressaccesstimesasfastas10nsavailable.Allbidirectional  
inputsandoutputsoftheIDT71V124areLVTTL-compatibleandoperation  
isfromasingle3.3Vsupply.Fullystaticasynchronouscircuitryisused;  
no clocks or refreshes are required for operation.  
FunctionalBlockDiagram  
A0  
1,048,576-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A16  
8
8
I/O0 - I/O7  
I/O CONTROL  
.
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3873 drw 01  
FEBRUARY 2013  
1
©
DSC-3873/11  
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  

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