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71V124HSA10PH PDF预览

71V124HSA10PH

更新时间: 2024-02-07 11:27:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 77K
描述
Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, TSOP2-32

71V124HSA10PH 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSOP2
包装说明:TSOP2-32针数:32
Reach Compliance Code:unknown风险等级:5.78
最长访问时间:10 ns其他特性:ALSO OPERATES WITH 3V TO 3.6 V SUPPLY
JESD-30 代码:R-PDSO-G32长度:20.95 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
认证状态:COMMERCIAL座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NOT SPECIFIED端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

71V124HSA10PH 数据手册

 浏览型号71V124HSA10PH的Datasheet PDF文件第2页浏览型号71V124HSA10PH的Datasheet PDF文件第3页浏览型号71V124HSA10PH的Datasheet PDF文件第4页浏览型号71V124HSA10PH的Datasheet PDF文件第5页浏览型号71V124HSA10PH的Datasheet PDF文件第6页浏览型号71V124HSA10PH的Datasheet PDF文件第7页 
3.3V CMOS Static RAM  
1 Meg (128K x 8-Bit)  
Center Power &  
IDT71V124SA/HSA  
Ground Pinout  
Features  
Description  
128K x 8 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise  
TheIDT71V124isa1,048,576-bithigh-speedstaticRAMorganized  
as128Kx8.ItisfabricatedusingIDT’shigh-performance,high-reliability  
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-  
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-  
speedmemoryneeds. The JEDECcenterpower/GNDpinoutreduces  
noisegenerationandimprovessystemperformance.  
Equal access and cycle times  
– Commercial:10/12/15/20ns  
Industrial:10/12/15/20ns  
One Chip Select plus one Output Enable pin  
Inputs and outputs are LVTTL-compatible  
Single 3.3V supply  
Low power consumption via chip deselect  
Available in a 32-pin 300- and 400-mil Plastic SOJ, and  
32-pin Type II TSOP packages.  
TheIDT71V124has anoutputenablepinwhichoperates as fastas  
5ns, with address access times as fast as 9ns available. All bidirec-  
tionalinputs andoutputs oftheIDT71V124areLVTTL-compatibleand  
operation is from a single 3.3V supply. Fully static asynchronous  
circuitry is used; no clocks or refreshes are required for operation.  
FunctionalBlockDiagram  
A0  
1,048,576-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A16  
8
8
I/O0 - I/O7  
I/O CONTROL  
.
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3873 drw 01  
FEBRUARY 2007  
1
DSC-3873/09  
©2007-IntegratedDeviceTechnology,Inc.  

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