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71V124HSA20PHG PDF预览

71V124HSA20PHG

更新时间: 2024-09-24 08:48:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 115K
描述
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32

71V124HSA20PHG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ObsoleteReach Compliance Code:compliant
风险等级:5.84最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e3内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP32,.46
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.095 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

71V124HSA20PHG 数据手册

 浏览型号71V124HSA20PHG的Datasheet PDF文件第2页浏览型号71V124HSA20PHG的Datasheet PDF文件第3页浏览型号71V124HSA20PHG的Datasheet PDF文件第4页浏览型号71V124HSA20PHG的Datasheet PDF文件第5页浏览型号71V124HSA20PHG的Datasheet PDF文件第6页浏览型号71V124HSA20PHG的Datasheet PDF文件第7页 
3.3V CMOS Static RAM  
1 Meg (128K x 8-Bit)  
Center Power &  
IDT71V124SA/HSA  
Ground Pinout  
Features  
Description  
128K x 8 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise  
TheIDT71V124isa1,048,576-bithigh-speedstaticRAMorganized  
as128Kx8.ItisfabricatedusingIDT’shigh-performance,high-reliability  
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-  
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-  
speedmemoryneeds. The JEDECcenterpower/GNDpinoutreduces  
noisegenerationandimprovessystemperformance.  
Equal access and cycle times  
– Commercial:10/12/15/20ns  
Industrial:10/12/15/20ns  
One Chip Select plus one Output Enable pin  
Inputs and outputs are LVTTL-compatible  
Single 3.3V supply  
Low power consumption via chip deselect  
Available in a 32-pin 300- and 400-mil Plastic SOJ, and  
32-pin Type II TSOP packages.  
TheIDT71V124has anoutputenablepinwhichoperates as fastas  
5ns, with address access times as fast as 9ns available. All bidirec-  
tionalinputs andoutputs oftheIDT71V124areLVTTL-compatibleand  
operation is from a single 3.3V supply. Fully static asynchronous  
circuitry is used; no clocks or refreshes are required for operation.  
FunctionalBlockDiagram  
A0  
1,048,576-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A16  
8
8
I/O0 - I/O7  
I/O CONTROL  
.
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3873 drw 01  
OCTOBER 2008  
1
DSC-3873/09  
©2007-IntegratedDeviceTechnology,Inc.  

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