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71V016SA20BFG8 PDF预览

71V016SA20BFG8

更新时间: 2024-01-28 01:58:28
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
9页 116K
描述
3.3V CMOS Static RAM

71V016SA20BFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:CABGA
包装说明:BGA, BGA48,6X8,30针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.41
最长访问时间:20 ns其他特性:ALSO OPERATES WITH 3V TO 3.6 V SUPPLY
I/O 类型:COMMONJESD-30 代码:S-PBGA-B48
JESD-609代码:e1长度:7 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:48
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA48,6X8,30
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.34 mm最大待机电流:0.01 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.12 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:7 mm

71V016SA20BFG8 数据手册

 浏览型号71V016SA20BFG8的Datasheet PDF文件第3页浏览型号71V016SA20BFG8的Datasheet PDF文件第4页浏览型号71V016SA20BFG8的Datasheet PDF文件第5页浏览型号71V016SA20BFG8的Datasheet PDF文件第6页浏览型号71V016SA20BFG8的Datasheet PDF文件第8页浏览型号71V016SA20BFG8的Datasheet PDF文件第9页 
IDT71V016SA, 3.3V CMOS Static RAM  
1 Meg (64K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)  
t
WC  
ADDRESS  
t
AW  
CS  
(2)  
t
AS  
tCW  
t
BW  
BHE, BLE  
tWP  
tWR  
WE  
DATAOUT  
DATAIN  
t
DH  
t
DW  
DATAIN VALID  
3834 drw 09  
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)  
t
WC  
ADDRESS  
tAW  
CS  
(2)  
t
CW  
tAS  
tBW  
BHE, BLE  
t
WP  
tWR  
WE  
DATAOUT  
DATAIN  
tDH  
t
DW  
DATAIN VALID  
3834 drw 10  
NOTES:  
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.  
2. OEis continuously HIGH. If during a WEcontrolled write cycle OEis LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed  
on the bus for the required tDW. If OEis HIGH during aWE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.  
3. Duringthisperiod, I/Opinsareintheoutputstate, andinputsignalsmustnotbeapplied.  
4. Ifthe CSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.  
5. Transitionismeasured±200mVfromsteadystate.  
7

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