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7142LA20J8 PDF预览

7142LA20J8

更新时间: 2024-11-06 05:27:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 146K
描述
PLCC-52, Reel

7142LA20J8 数据手册

 浏览型号7142LA20J8的Datasheet PDF文件第2页浏览型号7142LA20J8的Datasheet PDF文件第3页浏览型号7142LA20J8的Datasheet PDF文件第4页浏览型号7142LA20J8的Datasheet PDF文件第5页浏览型号7142LA20J8的Datasheet PDF文件第6页浏览型号7142LA20J8的Datasheet PDF文件第7页 
IDT7132SA/LA  
IDT7142SA/LA  
HIGH SPEED  
2K x 8 DUAL PORT  
STATIC RAM  
MASTERIDT7132easilyexpands databus widthto16-or-more  
bits using SLAVE IDT7142  
Features  
High-speed access  
On-chip port arbitration logic (IDT7132 only)  
BUSY output flag on IDT7132; BUSY input on IDT7142  
Battery backup operation 2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC  
packages  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
– Commercial:20/25/35/55/100ns(max.)  
Industrial:25ns (max.)  
Military:25/35/55/100ns(max.)  
Low-power operation  
IDT7132/42SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT7132/42LA  
Active:325mW(typ.)  
Standby: 1mW (typ.)  
Green parts available, see ordering information  
Functional Block Diagram  
OER  
OEL  
CEL  
CER  
R/W  
L
R/WR  
I/OOL-I/O7L  
I/OOR-I/O7R  
I/O  
Control  
I/O  
Control  
m
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
LOGIC  
CE  
OE  
R
R
CE  
OE  
L
L
R/WR  
R/W  
L
2692 drw 01  
NOTES:  
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270.  
IDT7142 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
SEPTEMBER 2010  
1
DSC-2692/19  
©2010IntegratedDeviceTechnology,Inc.  

7142LA20J8 替代型号

型号 品牌 替代类型 描述 数据表
7142SA20J IDT

完全替代

PLCC-52, Tube
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完全替代

PLCC-52, Reel
7142LA20JG IDT

完全替代

PLCC-52, Tube

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