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7142LA100L48B PDF预览

7142LA100L48B

更新时间: 2024-11-05 13:21:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 265K
描述
LCC-48, Tube

7142LA100L48B 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:LCC
包装说明:QCCN, LCC48,.56SQ,40针数:48
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.06
Is Samacsys:N最长访问时间:100 ns
其他特性:AUTOMATIC POWER-DOWN; BATTERY BACKUPI/O 类型:COMMON
JESD-30 代码:S-CQCC-N48JESD-609代码:e0
长度:14.3002 mm内存密度:16384 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端口数量:2端子数量:48
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:2KX8
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC48,.56SQ,40
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:3.048 mm
最大待机电流:0.004 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.14 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.016 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14.3002 mm
Base Number Matches:1

7142LA100L48B 数据手册

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HIGH SPEED  
2K x 8 DUAL PORT  
STATIC RAM  
IDT7132SA/LA  
IDT7142SA/LA  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
MASTERIDT7132easilyexpandsdatabuswidthto16-or-more  
bits using SLAVE IDT7142  
Features  
High-speed access  
On-chip port arbitration logic (IDT7132 only)  
BUSY output flag on IDT7132; BUSY input on IDT7142  
Battery backup operation —2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC  
packages  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
– Commercial:20/25/35/55/100ns(max.)  
– Industrial: 25ns (max.)  
– Military:25/35/55/100ns(max.)  
Low-power operation  
IDT7132/42SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
– IDT7132/42LA  
Active:325mW(typ.)  
Standby: 1mW (typ.)  
Green parts available, see ordering information  
Functional Block Diagram  
OE  
R
OE  
CE  
R/W  
L
L
CER  
L
R/W  
R
I/OOL-I/O7L  
I/OOR-I/O7R  
I/O  
Control  
I/O  
Control  
m
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
LOGIC  
CE  
OE  
R/W  
R
R
CE  
OE  
R/W  
L
L
L
R
2692 drw 01  
NOTES:  
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270.  
IDT7142 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
JULY 2018  
1
DSC-2692/22  

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