IDT7133SA/LA
IDT7143SA/LA
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
Features
◆
◆
High-speed access
BUSY output flag on IDT7133; BUSY input on IDT7143
Fully asynchronous operation from either port
◆
◆
◆
◆
–
–
–
Military:25/35/45/55/70/90ns(max.)
Industrial:25/35/55ns(max.)
Commercial:20/25/35/45/55/70/90ns(max.)
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
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Low-power operation
–
IDT7133/43SA
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◆
Active:1150mW(typ.)
Standby: 5mW (typ.)
IDT7133/43LA
–
◆
Green parts available, see ordering information
Active:1050mW(typ.)
Standby: 1mW (typ.)
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Description
Versatile control for write: separate write control for lower
and upper byte of each port
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133is designedtobe usedas a stand-alone 16-bitDual-Port
On-chip port arbitration logic (IDT7133 only)
Functional Block Diagram
R/WRUB
R/WLUB
CER
CE
L
R/WLLB
R/WRLB
OE
R
OE
L
I/O8L - I/O15L
I/O0L - I/O7L
(1)
I/O8R - I/O15R
I/O
CONTROL
I/O
CONTROL
I/O0R - I/O7R
(1)
R
BUSY
BUSY
L
A
10R
A
10L
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
0L
A
0R
11
11
ARBITRATION
LOGIC
CE
R
CE
L
(IDT7133 ONLY)
2746 drw 01
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
OCTOBER 2008
1
DSC 2746/13
©2008IntegratedDeviceTechnology,Inc.