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7133SA55JI PDF预览

7133SA55JI

更新时间: 2024-11-29 06:29:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 311K
描述
PLCC-68, Tube

7133SA55JI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:PLCC
包装说明:0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68针数:68
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.06
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e0
长度:24.2062 mm内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:1功能数量:1
端口数量:2端子数量:68
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC68,1.0SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.572 mm最大待机电流:0.015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.315 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.2062 mmBase Number Matches:1

7133SA55JI 数据手册

 浏览型号7133SA55JI的Datasheet PDF文件第2页浏览型号7133SA55JI的Datasheet PDF文件第3页浏览型号7133SA55JI的Datasheet PDF文件第4页浏览型号7133SA55JI的Datasheet PDF文件第5页浏览型号7133SA55JI的Datasheet PDF文件第6页浏览型号7133SA55JI的Datasheet PDF文件第7页 
IDT7133SA/LA  
IDT7143SA/LA  
HIGH SPEED  
2K X 16 DUAL-PORT  
SRAM  
Features  
High-speed access  
MASTER IDT7133 easily expands data bus width to 32 bits  
or more using SLAVE IDT7143  
Military:35/55/70/90ns(max.)  
Industrial:25/55ns(max.)  
Commercial:20/25/35/45/55/70/90ns(max.)  
On-chip port arbitration logic (IDT7133 only)  
BUSY output flag on IDT7133; BUSY input on IDT7143  
Fully asynchronous operation from either port  
Battery backup operation–2V data retention  
TTL-compatible; single 5V (±10%) power supply  
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-  
pin TQFP  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Low-power operation  
IDT7133/43SA  
Active:1150mW(typ.)  
Standby: 5mW (typ.)  
IDT7133/43LA  
Active:1050mW(typ.)  
Standby: 1mW (typ.)  
Versatile control for write: separate write control for lower  
and upper byte of each port  
Green parts available, see ordering information  
Functional Block Diagram  
R/WRUB  
R/WLUB  
CER  
CE  
L
R/WLLB  
R/WRLB  
OE  
R
OE  
L
I/O8L - I/O15L  
I/O0L - I/O7L  
(1)  
I/O8R - I/O15R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0R - I/O7R  
(1)  
R
BUSY  
BUSY  
L
A
10R  
A
10L  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
0L  
A
0R  
11  
11  
ARBITRATION  
LOGIC  
CE  
R
CE  
L
(IDT7133 ONLY)  
2746 drw 01  
NOTE:  
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.  
IDT7143 (SLAVE): BUSY is input.  
JANUARY 2012  
1
DSC 2746/14  
©2013IntegratedDeviceTechnology,Inc.  

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