Datasheet > 70V9369L12PFG8

70V9369L12PFG8

更新时间： 2024-01-09 00:18:42

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	222K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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数据手册

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70V9369L12PFG8 数据手册

HIGH-SPEED 3.3V 16K x 18

SYNCHRONOUS PIPELINED

DUAL-PORTSTATICRAM

IDT70V9369L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

True Dual-Ported memory cells which allow simultaneous

◆

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

addressinputs

access of the same memory location

High-speed clock to data access

◆

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– Commercial:6/7.5/9/12ns(max.)

– Industrial:7.5ns(max.)

Low-poweroperation

◆

– 12ns cycle time, 83MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexedbusandbusmatchingcompatibility

LVTTL- compatible, single 3.3V ( 0.3V) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

– IDT70V9369L

◆

Active:500mW(typ.)

Standby:1.5mW(typ.)

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

Counter enable and reset features

◆

Available in a 100-pin Thin Quad Flatpack (TQFP)

Green parts available, see ordering information

Dual chip enables allow for depth expansion without

additionallogic

Functional Block Diagram

CE0L

CE1L

CE0R

CE1R

0/1

1b 0b

0a 1a

1a 0a

0b 1b

FT/PIPE

0/1

FT/PIPE

I/O9R-I/O17R

I/O0R-I/O8R

I/O9L-I/O17L

I/O0L-I/O8L

I/O

Control

I/O

Control

13R

13L

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CNTEN

CNTRST

5648 drw 01

FEBRUARY 2018

DSC-5648/6

12 3 4 5 6 7...17

中文翻译

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