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70V9369L9PRF PDF预览

70V9369L9PRF

更新时间: 2024-11-28 20:44:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 188K
描述
Dual-Port SRAM, 16KX18, 9ns, CMOS, PQFP128, 22 X 14 MM, 1.6 MM HEIGHT, TQFP-128

70V9369L9PRF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:128
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.55
最长访问时间:9 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:22 mm内存密度:294912 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:128字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX18封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

70V9369L9PRF 数据手册

 浏览型号70V9369L9PRF的Datasheet PDF文件第2页浏览型号70V9369L9PRF的Datasheet PDF文件第3页浏览型号70V9369L9PRF的Datasheet PDF文件第4页浏览型号70V9369L9PRF的Datasheet PDF文件第5页浏览型号70V9369L9PRF的Datasheet PDF文件第6页浏览型号70V9369L9PRF的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 16K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
IDT70V9369L  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6/7.5/9/12ns(max.)  
Industrial:7.5ns (max.)  
Full synchronous operation on both ports  
– 4ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
Low-power operation  
IDT70V9369L  
– 12ns cycle time, 83MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Active:500mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP)  
FunctionalBlockDiagram  
R/  
W
L
L
R/  
W
R
R
UB  
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
OE  
L
L
LB  
OE  
R
R
1b 0b  
0a 1a  
1a 0a  
a
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
b
a
FT/PIPE  
R
I/O9R-I/O17R  
I/O0R-I/O8R  
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O  
Control  
I/O  
Control  
A
13R  
0R  
R
R
A
13L  
0L  
L
L
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
A
MEMORY  
ARRAY  
CLK  
CLK  
ADS  
ADS  
CNTEN  
R
CNTEN  
L
CNTRST  
R
CNTRST  
L
5648 drw 01  
OCTOBER 2008  
1
©2008 IntegratedDeviceTechnology,Inc.  
DSC-5648/3  

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