Datasheet > 70V9389L12PFGI8

70V9389L12PFGI8

更新时间： 2024-11-29 00:51:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	251K
描述
SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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数据手册

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70V9389L12PFGI8 数据手册

HIGH-SPEED 3.3V

64K x18/x16

IDT70V9389/289L

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

– Industrial: 9ns (max.)

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

addressinputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

– 12ns cycle time, 83MHz operation in Pipelined output

mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Low-power operation

– IDT70V9389/289L

Active:500mW(typ.)

Standby: 1.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 128-pin Thin Quad Flatpack (TQFP) and

100-pin Thin Quad Flatpack (TQFP)

Green parts available, see ordering information

◆

LVTTL- compatible, single 3.3V ( 0.3V) power supply

Functional Block Diagram

CE0L

CE0R

CE1L

CE1R

0/1

1b 0b

0a 1a

1a 0a

0b 1b

FT/PIPE

0/1

FT/PIPER

(2)

(1)

I/O9L-I/O17L

I/O9R-I/O17R

I/O

Control

(1)

I/O0R-I/O8R

I/O0L-I/O8L

15R

15L

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CNTEN

ADS

CNTEN

CNTRST

4856 drw 01

NOTES:

1. I/O0X - I/O7X for IDT70V9289.

2. I/O8X - I/O15X for IDT70V9289.

MARCH 2018

DSC-4856/9

12 3 4 5 6 7...19

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