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70V7599S200BFG PDF预览

70V7599S200BFG

更新时间: 2022-12-29 21:43:09
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 755K
描述
HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

70V7599S200BFG 数据手册

 浏览型号70V7599S200BFG的Datasheet PDF文件第6页浏览型号70V7599S200BFG的Datasheet PDF文件第7页浏览型号70V7599S200BFG的Datasheet PDF文件第8页浏览型号70V7599S200BFG的Datasheet PDF文件第10页浏览型号70V7599S200BFG的Datasheet PDF文件第11页浏览型号70V7599S200BFG的Datasheet PDF文件第12页 
IDT70V7599S  
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 150mV)  
70V7599S200(7) 70V7599S166(6)  
70V7599S133  
Com'l  
Com'l Only  
Com'l  
& Ind  
& Ind  
Symbol  
Parameter  
Test Condition  
Version  
COM'L  
Typ.(4)  
Max.  
950  
Typ.(4)  
Max.  
790  
830  
340  
355  
640  
660  
30  
Typ.(4)  
550  
550  
250  
250  
460  
460  
10  
Max. Unit  
IDD  
Dynamic Operating  
Current (Both  
mA  
mA  
mA  
mA  
mA  
CE and CE = VIL  
,
OutLputs DisaRbled,  
S
S
S
S
S
S
S
S
815  
675  
675  
275  
275  
515  
515  
10  
645  
675  
295  
310  
520  
545  
30  
____  
____  
(1)  
IND  
Ports Active)  
f = fMAX  
ISB1  
Standby Current  
(Both Ports - TTL  
Level Inputs)  
CE  
L
= CE  
R
= VIH  
COM'L  
IND  
340  
410  
(1)  
f = fMAX  
____  
____  
(3)  
ISB2  
Standby Current  
(One Port - TTL  
Level Inputs)  
CE"A" = VIL and CE"B" = VIH  
COM'L  
IND  
690  
770  
Active Port Outputs Disabled,  
____  
____  
(1)  
f=fMAX  
ISB3  
Full Standby Current  
(Both Ports - CMOS  
Level Inputs)  
Both Ports CE  
IN > VDDQ - 0.2V or VIN < 0.2V,  
f = 0(2)  
L and CER > VDDQ - 0.2V,  
COM'L  
IND  
10  
30  
V
____  
____  
10  
40  
10  
40  
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)  
ISB4  
Full Standby Current  
(One Port - CMOS  
Level Inputs)  
COM'L  
IND  
S
S
690  
770  
515  
515  
640  
660  
460  
460  
520  
545  
V
IN > VDDQ - 0.2V or VIN < 0.2V,  
Active Port, Outputs Disabled,  
____  
____  
(1)  
f = fMAX  
5626 tbl 09  
NOTES:  
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input  
levels of GND to 3V.  
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.  
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".  
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).  
5. CEX = VIL means CE0X = VIL and CE1X = VIH  
CEX = VIH means CE0X = VIH or CE1X = VIL  
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V  
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X < 0.2V  
"X" represents "L" for left port or "R" for right port.  
6. 166MHz Industrial Temperature not available in BF208 package.  
7. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC256 package only.  
6.42  
9

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