HIGH-SPEED 3.3V
256/128K x 18
SYNCHRONOUS
IDT70V3319/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
◆
◆
◆
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/FT option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V ( 150mV) power supply
for core
LVTTL compatible, selectable 3.3V ( 150mV) or 2.5V
( 100mV) power supply for I/Os and control signals on
each port
◆
◆
◆
◆
◆
◆
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
GridArray
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package
◆
◆
◆
Green parts available, see ordering information
Functional Block Diagram
UBL
UBR
LBL
LBR
FT/PIPE
L
1b 0b
b
1a 0a
a
0a 1a
a
0b 1b
b
FT/PIPER
1/0
1/0
R/WL
R/WR
CE0L
CE0R
1
1
CE1R
CE1L
B
B
B B
0
0
W W
W W
0
L
1
L
1
0
R
R
1/0
1/0
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
L
OER
,
0a 1a
0b 1b
ba
1b 0b 1a 0a
ab
0/1
FT/PIPE
L
0/1
FT/PIPER
256K x 18
MEMORY
ARRAY
Din_L
I/O0R - I/O17R
I/O0L - I/O17L
Din_R
,
CLKR
CLKL
(1)
L
(1)
A
17L
A
A
17R
Counter/
Address
Reg.
Counter/
Address
Reg.
A0L
0R
ADDR_R
ADDR_L
REPEAT
ADS
CNTEN
REPEAT
ADS
CNTEN
R
R
L
R
L
5623 tbl 01
TDI
TCK
TMS
TRST
NOTE:
1. A17 is a NC for IDT70V3399.
JTAG
TDO
JUNE 2018
1
DSC 5623/11
©2018 Integrated Device Technology, Inc.