Datasheet > 70V3379S5BFGI

70V3379S5BFGI

更新时间： 2024-09-20 00:38:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	729K
描述
HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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70V3379S5BFGI 数据手册

HIGH-SPEED 3.3V 32K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V3379S

Features:

– Data input, address, byte enable and control registers

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Self-timedwriteallowsfastcycletime

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

– Commercial:4.2/5/6ns(max.)

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

– Industrial: 5ns (max)

◆

Pipelined output mode

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

– Fast 4.2ns clock to data out

Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)

and 208-pin fine pitch Ball Grid Array, and 256-pin

Ball Grid Array

◆

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

Green parts available, see ordering information

FunctionalBlockDiagram

UBL

UBR

R/W

B B

W W

CE0L

CE0R

CE1L

CE1R

OER

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

32K x 18

MEMORY

ARRAY

I/O0R - I/O17R

I/O0 L - I/O1 7 L

Din_L

Din_R

CLK

A_14L

A_0L

A_14R

A_0R

Counter/

Address

Reg.

Counter/

Address

Reg.

ADDR_L

ADDR_R

CNTRST

ADS

CNTEN

4833 tbl 01

AUGUST 2015

DSC 4833/13

12 3 4 5 6 7...17

中文翻译

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