IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
A
50
48
A
46
A
44
0L BUSY
42
40
38
36
11
10
09
08
07
A
4L
2L
L
M/S INT
R
A1R
A
3R
5L
6L
8L
53
A
52
A
49
47
A
45
INT
43
41
BUSY
39
A
37
35
34
L
R
V
SS
A
4R
7L
9L
A
3L
1L
0R
A2R
A
5R
6R
8R
55
A
54
A
32
33
A
A
7R
57
A
56
30
31
A
A
9R
11L
A
10L
12L
59
58
A
28
29
A
11R
A10R
V
DD
IDT70V06G
G68(4)
61
60
26
27
A
06
05
04
03
02
01
N/C
A
13L
V
SS
12R
13R
68-Pin PGA
Top View(5)
63
SEM
62
24
N/C
25
A
L
CE
L
65
OE
64
22
SEM
23
21
R
CE
R
L
R/W
L
67
I/O0L
66
20
OE
R
R/W
R
N/C
1
3
5
V
7
I/O7L
9
V
68
11
I/O1R
13
V
15
18
19
I/O1L I/O2L I/O4L
SS
SS
DD I/O4R I/O7R N/C
2
4
6
8
10
12
14
16 17
I/O5L
I/O3L
I/O6L
VDD I/O0R I/O2R I/O3R I/O5R I/O6R
A
B
C
D
E
F
G
H
J
K
L
INDEX
2942 drw 04
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L - A13L
I/O0L - I/O7L
SEM
INT
BUSY
A
0R - A13R
I/O0R - I/O7R
SEM
INT
BUSY
M/S
Data Input/Output
Semaphore Enable
Interrupt Flag
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power (3.3V)
V
V
DD
SS
Ground (0V)
2942 tbl 01
6.42
3