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70V06L15GGI8 PDF预览

70V06L15GGI8

更新时间: 2022-12-29 19:49:37
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
23页 207K
描述
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM

70V06L15GGI8 数据手册

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IDT70V06S/L  
High-Speed 3.3V 16K x 8 Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
This device provides two independent ports with separate control,  
address,andI/Opinsthatpermitindependent,asynchronousaccessfor  
reads or writes to any location in memory. An automatic power down  
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter  
a very low standby power mode.  
Fabricated using CMOS high-performance technology, these de-  
vices typically operate on only 400mW of power.  
The IDT70V06 is packaged in a ceramic 68-pin PGA and PLCC  
and a 64-pin thin quad flatpack (TQFP).  
Description  
The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The  
IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port  
Static RAM or as a combination MASTER/SLAVE Dual-Port Static  
RAM for 16-bit-or-more word systems. Using the IDT MASTER/  
SLAVE Dual-Port Static RAM approach in 16-bit or wider memory  
system applications results in full-speed, error-free operation without  
the need for additional discrete logic.  
Pin Configurations(1,2,3)  
INDEX  
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61  
60  
I/O2L  
I/O3L  
I/O4L  
I/O5L  
A
A
A
A
A
A
5L  
4L  
3L  
2L  
1L  
0L  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
59  
58  
57  
56  
55  
V
SS  
I/O6L  
I/O7L  
IDT70V06J  
J68(4)  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
INT  
L
VDD  
BUSY  
L
68-Pin PLCC  
Top View(5)  
V
SS  
V
SS  
I/O0R  
I/O1R  
I/O2R  
M/S  
BUSY  
R
INT  
R
V
DD  
A
A
A
A
A
0R  
I/O3R  
I/O4R  
I/O5R  
I/O6R  
1R  
2R  
3R  
4R  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
2942 drw 02  
INDEX  
1
2
3
4
5
6
A
A
A
A
A
4L  
3L  
2L  
1L  
0L  
48  
47  
46  
I/O2L  
I/O3L  
I/O4L  
I/O5L  
45  
44  
43  
42  
41  
40  
39  
38  
37  
V
SS  
INT  
L
I/O6L  
I/O7L  
70V06PF  
PN-64(4)  
7
8
9
BUSY  
L
V
DD  
V
SS  
64-Pin TQFP  
Top View(5)  
VSS  
M/S  
BUSY  
R
10  
11  
12  
I/O0R  
I/O1R  
I/O2R  
INT  
R
A
A
A
A
A
0R  
VDD  
13  
14  
15  
1R  
2R  
3R  
4R  
36  
35  
34  
33  
I/O3R  
I/O4R  
I/O5R  
NOTES:  
1. All VDD pins must be connected to power supply.  
2. All VSS pins must be connected to ground supply.  
16  
3. J68-1 package body is approximately .95 in x .95 in x .17 in  
PN-64 package body is approximately 14mm x 14mm x 1.4mm.  
4. This package code is used to reference the package diagram.  
5. This text does not indicate orientation of the actual part marking.  
2942 drw 03  
2

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