Datasheet > 70V06L15JGI

70V06L15JGI

更新时间： 2022-12-29 19:49:37

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	207K
描述
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM

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数据手册

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70V06L15JGI 数据手册

HIGH-SPEED 3.3V

16K x 8 DUAL-PORT

STATIC RAM

IDT70V06S/L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

– Commercial:15/20/25/35/55ns(max.)

– Industrial:20/25ns(max.)

Low-power operation

◆

– IDT70V06S

Active:400mW(typ.)

Standby: 3.3mW (typ.)

– IDT70V06L

Active:380mW(typ.)

Standby:660µW(typ.)

IDT70V06 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 3.3V ( 0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆

Green parts available, see ordering information

Functional Block Diagram

OEL

OER

CEL

CER

R/W

R/WR

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSY

13L

13R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INTR

M/S

(2)

INTL

2942 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

JUNE 2018

DSC-2942/11

6.07

12 3 4 5 6 7...23

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