HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
IDT70V06S/L
Features
◆
◆
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
◆
◆
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25ns (max.)
Low-power operation
◆
◆
◆
◆
◆
◆
– IDT70V06S
Active:400mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V06L
Active:380mW(typ.)
Standby:660µW(typ.)
◆
IDT70V06 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
OEL
OER
CEL
CER
R/W
L
R/WR
,
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
R
BUSY
L
BUSY
A
13L
A
13R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A0R
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
L
L
CE
OE
R/W
R
R
R
R/W
L
SEM
INTL
L
SEM
INTR
R
M/S
(2)
(2)
2942 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
OCTOBER 2008
1
©2008IntegratedDeviceTechnology,Inc.
DSC-2942/9
6.07