Datasheet > 70T653MS10BCGI

70T653MS10BCGI

更新时间： 2024-11-09 00:58:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
24页	705K
描述
HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

70T653MS10BCGI 数据手册

HIGH-SPEED 2.5V

512K x 36

IDT70T653M

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

Full on-chip hardware support of semaphore signaling

between ports

◆

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

– Commercial:10/12/15ns(max.)

– Industrial: 12ns (max.)

◆

RapidWrite Mode simplifies high-speed consecutive write

cycles

Sleep Mode Inputs on both ports

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Includes JTAG functionality

Dual chip enables allow for depth expansion without

external logic

◆

IDT70T653M easily expands data bus width to 72 bits or

more using the Busy Input when cascading more than one

device

Available in a 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Busy input for port contention management

Interrupt Flags

◆

Green parts available, see ordering information

Functional Block Diagram

BE3L

BE3R

BE2R

BE2L

BE1L

BE0L

BE1R

BE0R

B B B B B B B B

E E E E E E E E

3 2 1 0

R R R R

CE0L

CE1L

CE0R

CE1R

OEL

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_R

Dout27-35_R

Dout18-26_L

Dout27-35_L

512K x 36

MEMORY

ARRAY

I/O0L- I/O35L

Di n_L

Di n_R

I/O0R -I/O35R

18R

18L

Address

Decoder

Address

Decoder

ADDR_L

ADDR_R

CE0L

CE1L

ARBITRATION

CE0R

CE1R

TDI

TCK

TMS

TRST

INTERRUPT

SEMAPHORE

LOGIC

JTAG

TDO

R/W

BUSY

SEM

BUSY

SEM

(1)

INTL

INT

(2)

ZZR

CONTROL

LOGIC

ZZL

NOTES:

1. INT is non-tri-state totem-pole outputs (push-pull).

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode

5679 drw 01

pins themselves (ZZx) are not affected during sleep mode.

JUNE 2015

DSC-5679/6

12 3 4 5 6 7...24

中文翻译

下载PDF

与70T653MS10BCGI相关器件

型号	品牌	获取价格	描述	数据表
70T653MS10BCGI8	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T653MS12BCG	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T653MS12BCG8	IDT	获取价格	Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
70T653MS12BCGI	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T653MS12BCGI8	IDT	获取价格	Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
70T653MS15BCG	IDT	获取价格	Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
70T653MS15BCG8	IDT	获取价格	Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
70T653MS15BCGI	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T653MS15BCGI8	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T659	RENESAS	获取价格	128K x 36 Async, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's

与70T653MS10BCGI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

70T653MS10BCGI

70T653MS10BCGI 数据手册

与70T653MS10BCGI相关器件

与70T653MS10BCGI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

70T653MS10BCGI

70T653MS10BCGI 数据手册

与70T653MS10BCGI相关器件

与70T653MS10BCGI相关文章

您还可以找

您在本页遇到什么问题？