Datasheet > 70T35L20BF8

70T35L20BF8

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	251K
描述
CABGA-100, Reel

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数据手册

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70T35L20BF8 数据手册

HIGH-SPEED 2.5V

8/4K x 18 DUAL-PORT

8/4K x 16 DUAL-PORT

STATIC RAM

PRELIMINARY

IDT70T35/34L

IDT70T25/24L

Features

width to 36 bits (32 bits) or more using the Master/Slave

select when cascading more than one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

BUSY and Interrupt Flag

On-chip port arbitration logic

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

IDT70T35/34L (IDT70T25/24L)

Commercial: 20/25ns (max.)

Industrial: 25ns (max.)

Full on-chip hardware support of semaphore signaling

between ports

Low-power operation

IDT70T35/34L (IDT70T25/24L)

Active:200mW(typ.)

Standby: 600µW(typ.)

Fully asynchronous operation from either port

LVTTL-compatible, single 2.5V (±100mV) power supply

Available in a 100-pin Thin Quad Flatpack (TQFP) package

and 100-pin fine pitch Ball Grid Array (fpBGA)

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT70T35/34L (IDT70T25/24L) easily expands data bus

Functional Block Diagram

R/W

UBL

(5)

(4)

I/O9R-I/O17R

I/O9L-I/O17L

I/O

Control

I/O

Control

(4)

I/O0R-I/O8R

I/O0L-I/O8L

BUSY ^(2,3)

(2,3)

BUSY

(1)

12L

(1)

12R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INT

(3)

INTR

M/S

5639 drw 01

NOTES:

1. A12 is a NC for IDT70T34 and IDT70T24.

2. (MASTER): BUSY is output; (SLAVE): BUSY is input.

3. BUSY outputs and INT outputs are non-tri-stated push-pull.

4. I/O0x - I/O7x for IDT70T25/24.

5. I/O8x - I/O15x for IDT70T25/24.

DECEMBER 2002

DSC-5639/2

12 3 4 5 6 7...21

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