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70T35L25PFGI PDF预览

70T35L25PFGI

更新时间: 2024-02-28 10:58:05
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 251K
描述
Dual-Port SRAM, 8KX18, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100

70T35L25PFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:25 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
内存密度:147456 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:100
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX18
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):2.6 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

70T35L25PFGI 数据手册

 浏览型号70T35L25PFGI的Datasheet PDF文件第2页浏览型号70T35L25PFGI的Datasheet PDF文件第3页浏览型号70T35L25PFGI的Datasheet PDF文件第4页浏览型号70T35L25PFGI的Datasheet PDF文件第5页浏览型号70T35L25PFGI的Datasheet PDF文件第6页浏览型号70T35L25PFGI的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
8/4K x 18 DUAL-PORT  
8/4K x 16 DUAL-PORT  
STATIC RAM  
PRELIMINARY  
IDT70T35/34L  
IDT70T25/24L  
Features  
width to 36 bits (32 bits) or more using the Master/Slave  
select when cascading more than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
IDT70T35/34L (IDT70T25/24L)  
– Commercial: 20/25ns (max.)  
– Industrial: 25ns (max.)  
Full on-chip hardware support of semaphore signaling  
between ports  
Low-power operation  
– IDT70T35/34L (IDT70T25/24L)  
Active:200mW(typ.)  
Standby: 600µW(typ.)  
Fully asynchronous operation from either port  
LVTTL-compatible, single 2.5V (±100mV) power supply  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
and 100-pin fine pitch Ball Grid Array (fpBGA)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70T35/34L (IDT70T25/24L) easily expands data bus  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UBL  
UB  
LB  
CE  
OE  
R
R
R
LB  
CE  
OE  
L
L
L
,
(5)  
(5)  
(4)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(4)  
I/O0R-I/O8R  
I/O0L-I/O8L  
BUSY (2,3)  
L
(2,3)  
BUSY  
R
(1)  
12L  
(1)  
A
A
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
L
R
R
L
SEM  
R
SEM  
INT  
L
L
(3)  
(3)  
INTR  
M/S  
5639 drw 01  
NOTES:  
1. A12 is a NC for IDT70T34 and IDT70T24.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
4. I/O0x - I/O7x for IDT70T25/24.  
5. I/O8x - I/O15x for IDT70T25/24.  
DECEMBER 2002  
1
DSC-5639/2  
©2002 IntegratedDeviceTechnology,Inc.  

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