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7026L55GB PDF预览

7026L55GB

更新时间: 2024-11-08 20:08:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
18页 154K
描述
Dual-Port SRAM, 16KX16, 55ns, CMOS, CPGA84, 1.120 X 1.12 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84

7026L55GB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:PGA
包装说明:PGA, PGA84M,11X11针数:84
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.68
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:S-CPGA-P84JESD-609代码:e0
内存密度:262144 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:84
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:16KX16
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA84M,11X11
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
筛选级别:MIL-PRF-38535最大待机电流:0.01 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.27 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:20
Base Number Matches:1

7026L55GB 数据手册

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HIGH-SPEED  
IDT7026S/L  
16K X 16 DUAL-PORT  
STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
IDT7026 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA and 84-pin PLCC  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
– Commercial:15/20/25/35/55ns (max.)  
Industrial: 20/25/35/55ns (max.)  
Military: 20/25/35/55ns (max.)  
Low-power operation  
IDT7026S  
Active: 750mW (typ.)  
Standby: 5mW (typ.)  
IDT7026L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multi-  
plexed bus compatibility  
FunctionalBlockDiagram  
R/  
W
R
R
R/  
W
UBL  
L
UB  
LB  
CE  
OE  
L
LB  
CER  
OE  
R
L
L
R
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
(1,2)  
L
(1,2)  
R
BUSY  
BUSY  
A
13R  
A
13L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
A
0L  
14  
14  
ARBITRATION  
SEMAPHORE  
LOGIC  
CE  
L
CE  
R
SEMR  
SEM  
L
M/S  
2939 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs are non-tri-stated push-pull.  
JANUARY 2009  
1
DSC 2939/13  
©2009IntegratedDeviceTechnology,Inc.  

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