Datasheet > 7026L55JGB8

7026L55JGB8

更新时间： 2024-11-09 00:32:55

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	685K
描述
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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7026L55JGB8 数据手册

HIGH-SPEED

IDT7026S/L

16K X 16 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

IDT7026 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

– Military: 20/25/35/55ns (max.)

Low-power operation

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

◆

On-chip port arbitration logic

◆

Full on-chip hardware support of semaphore signaling

between ports

– IDT7026S

◆

Active: 750mW (typ.)

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA and 84-pin PLCC

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Standby: 5mW (typ.)

– IDT7026L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆

Separate upper-byte and lower-byte control for multi-

plexed bus compatibility

Green parts available, see ordering information

FunctionalBlockDiagram

UBL

CER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSY

13R

13L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

SEMAPHORE

LOGIC

CEL

CER

SEM

SEMR

M/S

2939 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

AUGUST 2015

DSC 2939/14

12 3 4 5 6 7...18

中文翻译

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