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7025S45J PDF预览

7025S45J

更新时间: 2024-10-29 05:19:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 187K
描述
PLCC-84, Tube

7025S45J 数据手册

 浏览型号7025S45J的Datasheet PDF文件第2页浏览型号7025S45J的Datasheet PDF文件第3页浏览型号7025S45J的Datasheet PDF文件第4页浏览型号7025S45J的Datasheet PDF文件第5页浏览型号7025S45J的Datasheet PDF文件第6页浏览型号7025S45J的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7025S/L  
8K x 16 DUAL-PORT  
STATIC RAM  
IDT7025 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Battery backup operation—2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin  
Quad Flatpack  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Military:20/25/35/55/70ns(max.)  
– Industrial: 55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
– IDT7025S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
– IDT7025L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
FunctionalBlockDiagram  
R/W  
R
R
R/W  
L
L
UB  
UB  
LB  
CE  
OE  
L
L
L
LBR  
CER  
OER  
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
(1,2)  
(1,2)  
R
BUSY  
BUSY  
L
A
12R  
0R  
A
12L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
L
R
L
R
SEM  
L
SEM  
R
(2)  
(2)  
INT  
R
M/S  
INT  
L
2683 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JULY 2012  
1
DSC 2683/11  
©2012IntegratedDeviceTechnology,Inc.  

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