Datasheet > 7025S35JB

7025S35JB

更新时间： 2024-10-29 05:26:19

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
22页	178K
描述
Dual-Port SRAM, 8KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84

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中文翻译

获取价格

数据手册

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7025S35JB 数据手册

HIGH-SPEED

IDT7025S/L

8K x 16 DUAL-PORT

STATIC RAM

◆

IDT7025 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:20/25/35/55/70ns(max.)

– Industrial:55ns (max.)

◆

– Commercial:15/17/20/25/35/55ns(max.)

Low-power operation

◆

– IDT7025S

◆

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7025L

Active:750mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

bus compatibility

FunctionalBlockDiagram

R/W

CER

OER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSY

12R

12L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

M/S

INT

2683 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

OCTOBER 2008

DSC 2683/10

12 3 4 5 6 7...22

中文翻译

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