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7024L20GGI8 PDF预览

7024L20GGI8

更新时间: 2024-11-07 00:31:47
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 192K
描述
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

7024L20GGI8 技术参数

生命周期:Active包装说明:PGA,
Reach Compliance Code:compliant风险等级:5.77
最长访问时间:20 nsJESD-30 代码:S-CPGA-P84
JESD-609代码:e3长度:27.94 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端子数量:84字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX16封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
座面最大高度:5.207 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR宽度:27.94 mm
Base Number Matches:1

7024L20GGI8 数据手册

 浏览型号7024L20GGI8的Datasheet PDF文件第2页浏览型号7024L20GGI8的Datasheet PDF文件第3页浏览型号7024L20GGI8的Datasheet PDF文件第4页浏览型号7024L20GGI8的Datasheet PDF文件第5页浏览型号7024L20GGI8的Datasheet PDF文件第6页浏览型号7024L20GGI8的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7024S/L  
4K x 16 DUAL-PORT  
STATIC RAM  
IDT7024 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin  
Quad Flatpack  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts availble, see ordering information  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:20/25/35/55/70ns(max.)  
Industrial:55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
IDT7024S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7024L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
FunctionalBlockDiagram  
R/W  
L
R/W  
R
R
UB  
UBL  
LB  
CE  
OE  
L
L
L
LBR  
CE  
R
R
OE  
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
BUSY (1,2)  
L
BUSYR  
(1,2)  
A
11R  
0R  
A
11L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
12  
12  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
L
R
R
L
SEM  
R
SEM  
L
(2)  
INT (2)  
L
M/S  
INTR  
2740 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JUNE 2013  
1
DSC 2740/14  
©2013IntegratedDeviceTechnology,Inc.  

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