Datasheet > 7006L17JGB8

7006L17JGB8

更新时间： 2024-11-12 00:32:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	196K
描述
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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7006L17JGB8 数据手册

HIGH-SPEED

IDT7006S/L

16K x 8 DUAL-PORT

STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

◆

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Features

◆

True Dual-Ported memory cells which allow simultaneous

◆

reads of the same memory location

High-speed access

◆

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Devices are capable of withstanding greater than 2001V

electrostatic discharge

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin

TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

– Military:20/25/35/55/70ns(max.)

– Industrial: 55ns (max.)

◆

– Commercial:15/17/20/25/35/55ns(max.)

Low-power operation

◆

– IDT7006S

◆

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7006L

Active:700mW(typ.)

Standby: 1mW (typ.)

IDT7006 easily expands data bus width to 16 bits or more

◆

Green parts available, see ordering information

using the Master/Slave select when cascading more than

one device

FunctionalBlockDiagram

OER

OEL

CER

CEL

R/W

R/WR

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

BUSY ^(1,2)

(1,2)

BUSY

13L

13R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

SEM ₍₂₎

M/S

(2)

INT

INTR

2739 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

JULY 2018

DSC- 2739/18

12 3 4 5 6 7...21

中文翻译

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