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7006L20GGI8 PDF预览

7006L20GGI8

更新时间: 2024-02-03 18:42:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 196K
描述
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

7006L20GGI8 技术参数

生命周期:Active包装说明:PGA,
Reach Compliance Code:compliant风险等级:5.6
最长访问时间:20 nsJESD-30 代码:X-PPGA-P68
内存密度:131072 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端子数量:68字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX8封装主体材料:PLASTIC/EPOXY
封装代码:PGA封装形状:UNSPECIFIED
封装形式:GRID ARRAY并行/串行:PARALLEL
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:PIN/PEG端子位置:PERPENDICULAR
Base Number Matches:1

7006L20GGI8 数据手册

 浏览型号7006L20GGI8的Datasheet PDF文件第2页浏览型号7006L20GGI8的Datasheet PDF文件第3页浏览型号7006L20GGI8的Datasheet PDF文件第4页浏览型号7006L20GGI8的Datasheet PDF文件第5页浏览型号7006L20GGI8的Datasheet PDF文件第6页浏览型号7006L20GGI8的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7006S/L  
16K x 8 DUAL-PORT  
STATIC RAM  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Devices are capable of withstanding greater than 2001V  
electrostatic discharge  
Battery backup operation—2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin  
TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
– Military:20/25/35/55/70ns(max.)  
– Industrial: 55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
– IDT7006S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
– IDT7006L  
Active:700mW(typ.)  
Standby: 1mW (typ.)  
IDT7006 easily expands data bus width to 16 bits or more  
Green parts available, see ordering information  
using the Master/Slave select when cascading more than  
one device  
FunctionalBlockDiagram  
OER  
OEL  
CER  
CEL  
R/W  
L
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
BUSY  
R
A
13L  
A
13R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
0R  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
SEM  
R
SEM (2)  
L
M/S  
(2)  
INT  
L
INTR  
2739 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JULY 2018  
1
©2018 Integrated Device Technology, Inc.  
DSC- 2739/18  

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