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5V19EE901NLGI8 PDF预览

5V19EE901NLGI8

更新时间: 2024-10-28 07:51:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器时钟发生器逻辑集成电路石英晶振压控振荡器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
35页 734K
描述
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

5V19EE901NLGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:5V输入调节:MUX
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:7最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:0.9 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:5 mm最小 fmax:500 MHz
Base Number Matches:1

5V19EE901NLGI8 数据手册

 浏览型号5V19EE901NLGI8的Datasheet PDF文件第6页浏览型号5V19EE901NLGI8的Datasheet PDF文件第7页浏览型号5V19EE901NLGI8的Datasheet PDF文件第8页浏览型号5V19EE901NLGI8的Datasheet PDF文件第10页浏览型号5V19EE901NLGI8的Datasheet PDF文件第11页浏览型号5V19EE901NLGI8的Datasheet PDF文件第12页 
IDT5V19EE901  
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
CLOCK SYNTHESIZER  
to enhance the profile of the spread spectrum waveform.  
Tssc = 14 + 2 = 16  
Profile:  
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ,  
SS_OFFSET + SDJ+1, etc.  
Nssc = 6 * 2 = 12  
Spread Spectrum Using Sinusoidal Profile  
Nssc * Tssc = 192  
Use Eq.10 to determine the value of the  
sigma-delta-encoded samples.  
2% = (Σ∆ * 100)/(64 * 48)  
Σ∆ = 61.4  
Either round up or down to the nearest integer value.  
Therefore, we end up with 61 or 62 for sigma-delta-encoded  
samples. Since the sigma-delta-encoded samples must not  
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within  
the limits. It is the discretion of the user to define the shape  
of the profile that is better suited for the intended application.  
Using Eq. 9 again, the actual spread for the  
sigma-delta-encoded samples of 56 and 57 are 1.99% and  
2.02%, respectively.  
Use Eq.10 to determine if the X2 bit needs to be set;  
Amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1  
Example  
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center  
spread of 2%. Find the necessary spread spectrum  
register settings.  
Therefore, the X2 = '0 '. The dither bit is left to the discretion  
of the user.  
The example above was of a center spread using spread  
spectrum. For down spread, the nominal M value can be set  
one integer value lower to 47.  
Since the spread is center, the SS_OFFSET can be set to  
'0'. Solve for the nominal M value; keep in mind that the  
nominal M should be chosen to maximize  
Note that the IDT5V19EE901 should not be programmed  
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to  
prevent an unstable state in the modulator.  
the VCO. Start with D = 1, using Eq.6 and Eq.7.  
MNOM = 1200MHz / 25MHz = 48  
The PLL loop bandwidth must be at least 10x the  
modulation frequency along with higher damping (larger  
ωuz) to prevent the spread spectrum from being filtered and  
reduce extraneous noise. Refer to the LOOP FILTER  
section for more detail on ωuz. The A[3:0] must be used for  
spread spectrum, even if the total multiplier value is an even  
integer.  
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we  
have the nominal M value, we can determine TSSC and  
NSSC by using Eq.8.  
Nssc * Tssc = 25MHz / (33KHz * 4) = 190  
However, using Eq. 2 and Eq.3, we find that the closest  
value is when TSSC = 14 and NSSC = 6. Keep in mind to  
maximize the number of samples used  
IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
9
IDT5V19EE901 REV K 022310  

5V19EE901NLGI8 替代型号

型号 品牌 替代类型 描述 数据表
5V19EE901NLGI IDT

完全替代

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

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