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5V19EE901NLGI8 PDF预览

5V19EE901NLGI8

更新时间: 2024-10-28 07:51:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器时钟发生器逻辑集成电路石英晶振压控振荡器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
35页 734K
描述
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

5V19EE901NLGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:5V输入调节:MUX
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:7最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:0.9 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:5 mm最小 fmax:500 MHz
Base Number Matches:1

5V19EE901NLGI8 数据手册

 浏览型号5V19EE901NLGI8的Datasheet PDF文件第7页浏览型号5V19EE901NLGI8的Datasheet PDF文件第8页浏览型号5V19EE901NLGI8的Datasheet PDF文件第9页浏览型号5V19EE901NLGI8的Datasheet PDF文件第11页浏览型号5V19EE901NLGI8的Datasheet PDF文件第12页浏览型号5V19EE901NLGI8的Datasheet PDF文件第13页 
IDT5V19EE901  
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
CLOCK SYNTHESIZER  
Zero capacitor (Cz) = 196 pF + CZ* 217 pF  
Spread Spectrum Generation (PLL3)  
PLL3 support spread spectrum generation capability, which  
users have the option of turning on and off. Spread  
spectrum profile, frequency, and spread are fully  
programmable (within limits). The technique is different from  
that used in PLL0. The programmable spread spectrum  
generation parameters are SS_D3[7:0], SSVCO[15:0],  
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the  
memory address range of 0x4C to 0x85 for PLL3. The  
spread spectrum generation on PLL3 can be  
Pole capacitor (Cp) = 15 pF  
Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA  
VCO gain (KVCO) = 900 MHz/V * 2π  
The following equations govern how the loop filter is set for  
PLL3:  
enabled/disabled using the SSENB bit. To enable spread  
spectrum, set SSENB = '1'.  
For Non-Spread Spectrum Operation:  
(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))  
Resistor(Rz)=  
kOhms (Eq. 12)  
kOhms (Eq. 13)  
* RZ[0] +6*(1RZ[0])  
For Spread Enabled:  
Spread spectrum is configured using SS_D3(spread  
spectrum reference divide)  
For Spread Spectrum Operation:  
(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))  
F
IN  
(Eq. 10)  
=
SS_D3  
Resistor(Rz)=  
4 * F  
* RZ[0] +6*(1RZ[0])  
MOD  
and SSVCO (spread spectrum loop feedback counter).  
Zero capacitor (Cz) = 250 pF  
Pole capacitor (Cp) = 15 pF  
F
VCO  
( 1 + SS/400) + 5]  
(Eq. 11)  
SSVCO [0.5 *  
*
=
F
MOD  
For Non-Spread Spectrum Operation:  
SS is the total Spread Spectrum amount (I.e. center spread  
+0.5% has a total spread of 1.0% and down spread -0.5%  
has a total spread of 0.5%.)  
24* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))  
Charge  
A (Eq. 14)  
A (Eq. 14)  
=
pump (Ip)  
3+(5* IP[3]) +(11* IP[4])  
Loop Filter  
For Spread Spectrum Operation:  
The loop filter for each PLL can be programmed to optimize  
the jitter performance. The low-pass frequency response of  
the PLL is the mechanism that dictates the jitter transfer  
characteristics. The loop bandwidth can be extracted from  
the jitter transfer. A narrow loop bandwidth is good for jitter  
attenuation while a wide loop bandwidth is best for low-jitter  
frequency generation. The specific loop filter components  
that can be programmed are the resistor via the RZ[3:0] bits,  
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and  
the charge pump current via the IP[2:0] bits (for PLL0, PLL1  
and PLL2) or IP[3:0] (for PLL3).  
12* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))  
Charge  
pump (Ip)  
=
27+(5* IP[3]) +(11* IP[4])  
VCO gain (KVCO) = 900 MHz/V * 2π  
The following equations govern how the loop filter is set for  
PLL0 - PLL2:  
Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0  
kOhm  
IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
10  
IDT5V19EE901 REV K 022310  

5V19EE901NLGI8 替代型号

型号 品牌 替代类型 描述 数据表
5V19EE901NLGI IDT

完全替代

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

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