5V19EE901NLGI8

更新时间： 2024-01-26 05:29:56

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器时钟发生器逻辑集成电路石英晶振压控振荡器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
35页	734K
描述
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

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技术参数
数据手册

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5V19EE901NLGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	VFQFPN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.81
系列：	5V	输入调节：	MUX
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	7	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.075 ns	座面最大高度：	0.9 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	最小 fmax：	500 MHz
Base Number Matches：	1

5V19EE901NLGI8 数据手册

IDT5V19EE901

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

CLOCK SYNTHESIZER

clocks are at different frequencies, the device will always

remain on the primary clock unless it is absent for two

secondary clock cycles. The secondary clock must always

run at a frequency less than or equal to the primary clock

frequency.

Q[6:0]

Output Divider

111 1111

Disabled

Reference Divider, Feedback Divider, and

Output Divider

<111 1111

/((Q[6:0] + 2) * 2)

Each PLL incorporates a 7-bit reference divider (D[6:0]) and

a 12-bit feedback divider (N[11:0]) that allows the user to

generate four unique non-integer-related frequencies. Each

output divide supports 8-bit output-divider (PM and Q[7:0]).

The following equation governs how the output frequency is

calculated.

Note that the actual 7-bit Q-divider value has a 2 added to

the integer value Q and the outputs are routed through

another div/2 block. The output divider should never be

disabled unless the output bank will never be used during

normal operation. The output frequency range for LVTTL

outputs are from 4.9KHz to 200MHz. The output frequency

for LVPECL/LVDS/HCSL outputs range from 4.9KHz to

500MHz.

F *

F_OUT

( _D)

(Eq. 1)

ODIV

Spread Spectrum Generation (PLL0)

Where FIN is the reference frequency, M is the total

feedback-divider value, D is the reference divider value,

ODIV is the total output-divider value, and FOUT is the

resulting output frequency.

PLL0 supports spread spectrum generation capability,

which users have the option of turning on or off. Spread

spectrum profile, frequency, and spread amplitude are fully

programmable. The programmable spread spectrum

generation parameters are TSSC[3:0], NSSC[2:0],

SS_OFFSET[5:0], SD[3:0], DITH, and X2 bits. These bits

are in the memory address from 0xAC to 0xBD for PLL0.

The spread spectrum generation on PLL0 can be

enabled/disabled using the TSSC[3:0] bits. To enable

spread spectrum, set TSSC > '0' and set NSSC[2:0],

SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M

value) accordingly. To disable spread spectrum generation,

set TSSC = '0'.

For PLL0,

M = 2 * N + A + 1 (for A>0)

M = 2 * N (for A = 0)

For PLL1, PLL2 and PLL3,

M = N

TSSC[3:0]

PM and Q[6:0] are the bits used to program the 8-bit

output-dividers for outputs OUT1-6. OUT0 does not have

any output divide along its path. The 8-bit output-dividers

will bypass or divide down the output banks' frequency with

even integer values ranging from 2 to 256.

These bits are used to determine the number of

phase/frequency detector cycles per spread spectrum cycle

(ssc) steps. The modulation frequency can be calculated

with the TSSC bits in conjunction with the NSSC bits. Valid

TSSC integer values for the modulation frequency range

from 5 to 14. Values of 0 - 4 and 15 should not be used.

There is the option to choose between disabling the

output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider

by using the PM bit. If the output is disabled, it will be driven

High, Low or High Impedance, depending on OEM[1:0].

Each bank, except for OUT0, has a PM bit. When disabled,

no clocks will appear at the output of the divider, but will

remain powered on. The output divides selection table is

shown below.

NSSC[2:0]

These bits are used to determine the number of

delta-encoded samples used for a single quadrant of the

spread spectrum waveform. All four quadrants of the spread

spectrum waveform are mirror images of each other. The

modulation frequency is also calculated based on the NSSC

bits in conjunction with the TSSC bits. Valid NSSC integer

IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

IDT5V19EE901 REV K 022310

1...4 5 678 9 10...35

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