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598BCA000118DG PDF预览

598BCA000118DG

更新时间: 2024-09-16 18:58:39
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
28页 523K
描述
Oscillator, 10MHz Min, 810MHz Max, 810MHz Nom

598BCA000118DG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LCC8,.2X.28,100Reach Compliance Code:compliant
风险等级:5.57安装特点:SURFACE MOUNT
端子数量:8最大工作频率:810 MHz
最小工作频率:10 MHz标称工作频率:810 MHz
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC封装等效代码:LCC8,.2X.28,100
电源:3.3 V认证状态:Not Qualified
子类别:Other Oscillators最大压摆率:110 mA
标称供电电压:3.3 V表面贴装:YES
Base Number Matches:1

598BCA000118DG 数据手册

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Si598/Si599  
10–810 MHZ I2C PROGRAMMABLE XO/VCXO  
Features  
Programmable with 28 parts per  
trillion frequency resolution  
Integrated crystal provides stability  
and low phase noise  
Frequency changes up to  
±3500 ppm are glitchless  
I2C programmable output  
frequencies from 10 to 810 MHz  
0.5 ps RMS phase jitter  
Superior power supply rejection:  
0.3–0.4 ps additive jitter  
Available LVPECL, CMOS, LVDS,  
and CML outputs  
1.8, 2.5, or 3.3 V supply  
Pin- and register-compatible with  
Si570/571  
–40 to 85 °C operation  
Industry-standard 5x7 mm package  
Applications  
Ordering Information:  
See page 22.  
SONET / SDH / xDSL  
Ethernet / Fibre Channel  
3G SDI / HD SDI  
Multi-rate PLLs  
Multi-rate reference clocks  
Frequency margining  
Digital PLLs  
CPU / FPGA FIFO control  
Adaptive synchronization  
Agile RF local oscillators  
Pin Assignments:  
See page 21.  
Description  
(Top View)  
The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®  
circuitry to provide a low-jitter clock at any frequency. They are user-  
programmable to any output frequency from 10 to 810 MHz with 28 parts per  
SDA  
7
NC  
VDD  
1
2
3
6
5
4
2
trillion (PPT) resolution. The device is programmed via a 2-pin I C compatible  
serial interface. The wide frequency range and ultra-fine programming resolution  
make these devices ideal for applications that require in-circuit dynamic frequency  
adjustments or multi-rate operation with non-integer related rates. Using an  
integrated crystal, these devices provide stable low jitter frequency synthesis and  
replace multiple XOs, clock generators, and DAC controlled VCXOs.  
OE  
CLK–  
CLK+  
GND  
8
Functional Block Diagram  
SCL  
Si598  
VDD  
Power Supply Filtering  
OE  
SDA  
7
Fixed  
Frequency  
Oscillator  
Any Frequency  
DSPLL®  
10 to 810 MHz  
Clock Synthesis  
CLK+  
CLK–  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
Vc  
ADC  
I2C Interface  
(Si599)  
GND  
8
SCL  
SDA  
SCL  
GND  
Si599  
Rev. 1.0 11/11  
Copyright © 2011 by Silicon Laboratories  
Si598/Si599  

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