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5962-9950801QRX PDF预览

5962-9950801QRX

更新时间: 2024-02-14 20:36:18
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器输出元件
页数 文件大小 规格书
22页 953K
描述
LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20

5962-9950801QRX 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.6控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:LVT
JESD-30 代码:R-GDFP-F20负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.048 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
Prop。Delay @ Nom-Sup:4.7 ns传播延迟(tpd):5.1 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class V
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:BICMOS温度等级:MILITARY
端子形式:FLAT端子位置:DUAL
翻译:N/ABase Number Matches:1

5962-9950801QRX 数据手册

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SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003  
description/ordering information (continued)  
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE  
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
SN74LVTH240 . . . GQN OR ZQN PACKAGE  
(TOP VIEW)  
terminal assignments  
1
2
3
4
1
2
3
4
A
B
C
D
E
A
B
C
D
E
1A1  
1A2  
1A3  
1A4  
GND  
1OE  
2A4  
2Y3  
2A2  
2Y1  
V
2OE  
1Y1  
1Y2  
1Y3  
1Y4  
CC  
2Y4  
2A3  
2Y2  
2A1  
FUNCTION TABLE  
(each 4-bit buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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