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5962-9950901QRA PDF预览

5962-9950901QRA

更新时间: 2024-02-22 22:38:17
品牌 Logo 应用领域
德州仪器 - TI 锁存器逻辑集成电路输出元件信息通信管理驱动
页数 文件大小 规格书
16页 472K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

5962-9950901QRA 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.46控制类型:ENABLE LOW/HIGH
计数方向:UNIDIRECTIONAL系列:LVT
JESD-30 代码:R-GDFP-F20负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.048 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT APPLICABLE最大电源电流(ICC):5 mA
Prop。Delay @ Nom-Sup:4.4 ns传播延迟(tpd):5.1 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:2.54 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE翻译:N/A
宽度:6.92 mmBase Number Matches:1

5962-9950901QRA 数据手册

 浏览型号5962-9950901QRA的Datasheet PDF文件第2页浏览型号5962-9950901QRA的Datasheet PDF文件第3页浏览型号5962-9950901QRA的Datasheet PDF文件第4页浏览型号5962-9950901QRA的Datasheet PDF文件第5页浏览型号5962-9950901QRA的Datasheet PDF文件第6页浏览型号5962-9950901QRA的Datasheet PDF文件第7页 
ꢈ ꢋꢈ ꢌꢅ ꢍꢎꢆ ꢏ ꢐꢆꢍꢄ ꢆ ꢑꢍꢁꢀ ꢒꢍꢑꢓ ꢁꢆ ꢔꢌꢆ ꢕꢒ ꢓ ꢄꢍꢆꢐ ꢇ ꢓ  
ꢖ ꢗꢆ ꢇ ꢈ ꢌꢀꢆꢍꢆ ꢓ ꢏ ꢘꢆ ꢒ ꢘꢆ  
SCBS689H − MAY 1997 − REVISED OCTOBER 2003  
SN54LVTH373 . . . J OR W PACKAGE  
SN74LVTH373 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
D
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OLP  
CC  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
1
2
3
4
5
6
7
8
9
10  
V
CC  
= 3.3 V, T = 25°C  
A
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
Support Unregulated Battery Operation  
Down to 2.7 V  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
GND  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
SN54LVTH373 . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
3
2
1 20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
4
5
6
7
8
17  
16  
15  
14  
These octal latches are designed specifically for  
low-voltage (3.3-V) V  
operation, but with the  
CC  
capability to provide a TTL interface to a  
5-V system environment.  
9 10 11 12 13  
While the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74LVTH373DW  
SN74LVTH373DWR  
SN74LVTH373NSR  
SN74LVTH373DBR  
SN74LVTH373PW  
SN74LVTH373PWR  
SNJ54LVTH373J  
SOIC − DW  
LVTH373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH373  
LXH373  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
LXH373  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC - FK  
SNJ54LVTH373J  
SNJ54LVTH373W  
SNJ54LVTH373FK  
Tube  
SNJ54LVTH373W  
SNJ54LVTH373FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢏ ꢙ ꢚ ꢛ ꢜꢝ ꢞꢟ ꢠꢡ ꢟꢜ ꢢꢚ ꢣꢤ ꢥꢙ ꢠ ꢠꢜ ꢦꢗ ꢄꢌ ꢒꢑ ꢧ ꢌꢈꢨꢂ ꢈꢂꢊ ꢥꢣꢣ ꢚꢥ ꢛ ꢥ ꢢꢩ ꢠꢩꢛ ꢡ ꢥ ꢛ ꢩ ꢠꢩ ꢡꢠꢩ ꢝ  
ꢠ ꢩ ꢡ ꢠꢤ ꢙꢬ ꢜꢮ ꢥ ꢣꢣ ꢚꢥ ꢛ ꢥ ꢢ ꢩ ꢠ ꢩ ꢛ ꢡ ꢋ  
ꢞ ꢙꢣ ꢩꢡꢡ ꢜ ꢠꢪꢩ ꢛ ꢫꢤ ꢡꢩ ꢙ ꢜꢠꢩ ꢝꢋ ꢏ ꢙ ꢥꢣ ꢣ ꢜ ꢠꢪꢩ ꢛ ꢚꢛ ꢜ ꢝꢞꢟ ꢠꢡ ꢊ ꢚꢛ ꢜ ꢝꢞꢟ ꢠꢤꢜ ꢙ  
ꢜꢟ  
ꢩꢛ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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