5秒后页面跳转
捷配首页

Datasheet > 存储 > FIFO> 5962-9736101QYAX
5962-9736101QYAX PDF预览

5962-9736101QYAX

更新时间： 2024-01-26 14:37:02
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储先进先出芯片
页数 文件大小 规格书
18页 548K
描述
FIFO, 32KX9, 10ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32

阅读下载

中文翻译

获取价格

5962-9736101QYAX 技术参数

生命周期：Obsolete零件包装代码：QFJ
包装说明：QCCN,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.84
最长访问时间：10 ns其他特性：RETRANSMIT
周期时间：15 ns长度：13.97 mm
内存密度：294912 bit内存宽度：9
功能数量：1字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：32KX9可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形式：CHIP CARRIER并行/串行：PARALLEL
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class Q
座面最大高度：2.286 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
宽度：11.43 mmBase Number Matches：1

5962-9736101QYAX 数据手册

 浏览型号5962-9736101QYAX的Datasheet PDF文件第1页浏览型号5962-9736101QYAX的Datasheet PDF文件第3页浏览型号5962-9736101QYAX的Datasheet PDF文件第4页浏览型号5962-9736101QYAX的Datasheet PDF文件第5页浏览型号5962-9736101QYAX的Datasheet PDF文件第6页浏览型号5962-9736101QYAX的Datasheet PDF文件第7页 
CY7C4261  
CY7C4271  
entering or exiting the Empty and Almost Empty states, the  
flags are updated exclusively by the RCLK. The flags denoting  
Almost Full, and Full states are updated exclusively by WCLK.  
The synchronous flag architecture guarantees that the flags  
maintain their status for at least one cycle.  
Functional Description (continued)  
The CY7C4261/71 provides four status pins: Empty, Full,  
Programmable Almost Empty, and Programmable Almost Full.  
The Almost Empty/Almost Full flags are programmable to  
single word granularity. The programmable flags default to  
Empty + 7 and Full – 7.  
All configurations are fabricated using an advanced 0.5µ  
CMOS technology. Input ESD protection is greater than  
2001V, and latch-up is prevented by the use of guard rings.  
The flags are synchronous, i.e., they change state relative to  
either the read clock (RCLK) or the write clock (WCLK). When  
Pin Definitions  
Signal Name  
D0−8  
Description I/O  
Description  
Data Inputs  
I
O
I
Data Inputs for 9-bit bus.  
Q0−8  
Data Outputs  
Write Enable 1  
Data Outputs for 9-bit bus.  
WEN1  
The only write enable when device is configured to have programmable flags. Data  
is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.  
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH  
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.  
WEN2/LD  
Dual Mode Pin  
Write Enable 2  
Load  
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin  
operates as a control to write or read the programmable flag offsets. WEN1 must be LOW  
and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the  
FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD  
is held LOW to write or read the programmable flag offsets.  
REN1, REN2 Read Enable  
Inputs  
I
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to  
allow a read operation.  
WCLK  
Write Clock  
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH  
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable  
flag-offset register.  
RCLK  
Read Clock  
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the  
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable  
flag-offset register.  
EF  
Empty Flag  
Full Flag  
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.  
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.  
FF  
PAE  
Programmable  
Almost Empty  
When PAE is LOW, the FIFO is almost empty based on the almost empty offset  
value programmed into the FIFO. PAE is synchronized to RCLK.  
PAF  
RS  
Programmable  
Almost Full  
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value  
programmed into the FIFO. PAF is synchronized to WCLK.  
Reset  
Resets device to empty condition. A reset is required before an initial read or write  
operation after power-up.  
OE  
Output Enable  
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are  
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.  
Selection Guide  
7C4261/71-10  
7C4261/71-15  
7C4261/71-25  
7C4261/71-35  
Unit  
MHz  
ns  
Maximum Frequency  
100  
8
66.7  
10  
15  
4
40  
15  
25  
6
28.6  
20  
35  
7
Maximum Access Time  
Minimum Cycle Time  
10  
3
ns  
Minimum Data or Enable Set-up  
Minimum Data or Enable Hold  
Maximum Flag Delay  
ns  
0.5  
8
1
1
2
ns  
10  
35  
40  
15  
35  
40  
20  
35  
40  
ns  
Active Power Supply Commercial  
35  
40  
mA  
Current (ICC1  
)
Industrial/  
Military  
Document #: 38-06015 Rev. *C  
Page 2 of 18  
1234567...18

中文翻译

下载PDF

与5962-9736101QYAX相关器件

型号 品牌 获取价格 描述 数据表
5962-9736101QYX CYPRESS

获取价格

 		FIFO, 32KX9, 10ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32
5962-9745801QEA TI

获取价格

 		TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-
5962-9745801QEX TI

获取价格

 		TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-
5962-9745801QFA TI

获取价格

 		IC TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, D
5962-9750401MXA ETC

获取价格

 		Digital Filter
5962-9750401MXC ETC

获取价格

 		Digital Filter
5962-9750402MXA LOGIC

获取价格

 		Digital Filter, 10-Bit, CMOS, CPGA84, CERAMIC, PGA-84
5962-9750402MXC ETC

获取价格

 		Digital Filter
5962-9750402MXX WEDC

获取价格

 		IC 10-BIT, DSP-DIGITAL FILTER, CPGA84, CERAMIC, PGA-84, DSP Peripheral
5962-9750403MXA ETC

获取价格

 		Digital Filter

与5962-9736101QYAX相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证