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5962-9736101QYAX PDF预览

5962-9736101QYAX

更新时间： 2024-01-19 18:54:48
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储先进先出芯片
页数 文件大小 规格书
18页 548K
描述
FIFO, 32KX9, 10ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32

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5962-9736101QYAX 技术参数

生命周期：Obsolete零件包装代码：QFJ
包装说明：QCCN,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.84
最长访问时间：10 ns其他特性：RETRANSMIT
周期时间：15 ns长度：13.97 mm
内存密度：294912 bit内存宽度：9
功能数量：1字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：32KX9可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形式：CHIP CARRIER并行/串行：PARALLEL
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class Q
座面最大高度：2.286 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
宽度：11.43 mmBase Number Matches：1

5962-9736101QYAX 数据手册

 浏览型号5962-9736101QYAX的Datasheet PDF文件第1页浏览型号5962-9736101QYAX的Datasheet PDF文件第2页浏览型号5962-9736101QYAX的Datasheet PDF文件第3页浏览型号5962-9736101QYAX的Datasheet PDF文件第5页浏览型号5962-9736101QYAX的Datasheet PDF文件第6页浏览型号5962-9736101QYAX的Datasheet PDF文件第7页 
CY7C4261  
CY7C4271  
The number formed by the empty offset least significant bit  
register and empty offset most significant bit register is  
referred to as n and determines the operation of PAE. PAF is  
synchronized to the LOW-to-HIGH transition of RCLK by one  
flip-flop and is LOW when the FIFO contains n or fewer unread  
words. PAE is set HIGH by the LOW-to-HIGH transition of  
RCLK when the FIFO contains (n+1) or greater unread words.  
Table 1. Writing the Offset Registers  
WCLK[1]  
LD  
WEN  
Selection  
0
0
Empty Offset (LSB)  
Empty Offset (MSB)  
Full Offset (LSB)  
The number formed by the full offset least significant bit  
register and full offset most significant bit register is referred to  
as m and determines the operation of PAF. PAE is synchronized  
to the LOW-to-HIGH transition of WCLK by one flip-flop and is  
set LOW when the number of unread words in the FIFO is  
greater than or equal to CY7C4261 (16K-m) and CY7C4271  
(32K-m). PAF is set HIGH by the LOW-to-HIGH transition of  
WCLK when the number of available memory locations is  
greater than m.  
Full Offset (MSB)  
0
1
1
0
No Operation  
Write Into FIFO  
1
1
No Operation  
Table 2. Status Flags  
Number of Words in FIFO  
CY7C4261  
CY7C4271  
FF  
H
H
H
H
L
PAF  
H
PAE  
L
EF  
L
0
0
1 to n[2]  
1 to n[2]  
H
L
H
H
H
H
(n + 1) to (16384 − (m + 1))  
(16384 − m)[3] to 16383  
16384  
(n + 1) to (32768 − (m + 1))  
(32768 − m)[3] to 32767  
32768  
H
H
L
H
L
H
Width-Expansion Configuration  
Flag Operation  
Word width may be increased simply by connecting the corre-  
sponding input controls signals of multiple devices. A  
composite flag should be created for each of the end-point  
status flags (EF and FF). The partial status flags (PAEand PAF)  
can be detected from any one device. Figure 2 demonstrates  
a 18-bit word width by using two CY7C4261/71s. Any word  
width can be attained by adding additional CY7C4261/71s.  
The CY7C4261/71 devices provide four flag pins to indicate  
the condition of the FIFO contents. Empty, Full, PAE, and PAF  
are synchronous.  
Full Flag  
The Full Flag (FF) will go LOW when the device is full. Write  
operations are inhibited whenever FFis LOW regardless of the  
state of WEN1and WEN2/LD. FF is synchronized to WCLK, i.e.,  
it is exclusively updated by each rising edge of WCLK.  
When the CY7C4261/71 is in a Width-Expansion Configu-  
ration, the Read Enable (REN2) control input can be grounded  
(see Figure 2). In this configuration, the Write Enable 2/Load  
(WEN2/LD) pin is set to LOW at Reset so that the pin operates  
as a control to load and read the programmable flag offsets.  
Empty Flag  
The Empty Flag (EF) will go LOW when the device is empty.  
Read operations are inhibited whenever EF is LOW,  
regardless of the state of REN1 and REN2. EF is synchronized  
to RCLK, i.e., it is exclusively updated by each rising edge of  
RCLK.  
Notes:  
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.  
2. n = Empty Offset (n = 7 default value).  
3. m = Full Offset (m = 7 default value).  
Document #: 38-06015 Rev. *C  
Page 4 of 18  
1234567...18

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