41
CY7C341
192-Macrocell MAX® EPLD
Features
Programmable Interconnect Array
• 192 macrocells in 12 logic array blocks (LABs)
• Eight dedicated inputs, 64 bidirectional I/O pins
• 0.8-micron double-metal CMOS EPROM technology
• Programmable interconnect array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
• 384 expander product terms
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array config-
uration, simplifies design by assuring that internal signal
skews or races are avoided. The result is ease of design imple-
mentation, often in a single pass, without the multiple internal
logic placement and routing iterations required for a program-
mable gate array to achieve design timing objectives.
• Available in 84-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C341 is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the devices to accom-
modate a variety of independent logic functions.
The 192 macrocells in the CY7C341 are divided into 12 LABs,
16 per LAB. There are 384 expander product terms, 32 per
LAB, to be used and shared by the macrocells within each
LAB. Each LAB is interconnected with a programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
Timing Delays
Timing delays within the CY7C341 may be easily determined
using Warp™, Warp Professional™, or Warp Enterprise™
software. The CY7C341 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
The speed and density of the CY7C341 allows them to be
used in a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 37 times the function-
ality of 20-pin PLDs, the CY7C341 allows the replacement of
over 75 TTL devices. By replacing large amounts of logic, the
CY7C341 reduces board space and part count, and increases
system reliability.
Design Recommendations
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND, directly
at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, eight
macrocells are connected to I/O pins and eight are buried,
while for LABs B, C, D, E, H, I, J, and K, four macrocells are
connected to I/O pins and 12 are buried. Moreover, in addition
to the I/O and buried macrocells, there are 32 single product
term logic expanders in each LAB. Their use greatly enhances
the capability of the macrocells without increasing the number
of product terms in each macrocell.
Design Security
The CY7C341 contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the device. The
CY7C341 is fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal
logic elements thus ensuring 100% programming yield.
Logic Array Blocks
There are 12 logic array blocks in the CY7C341. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Externally, the CY7C341 provides eight dedicated inputs, one
of which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirec-
tional data flow.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03034 Rev. *A
Revised December 11, 2001
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