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5962-8768102VEA PDF预览

5962-8768102VEA

更新时间: 2024-11-23 22:34:11
品牌 Logo 应用领域
德州仪器 - TI 稳压器开关式稳压器或控制器电源电路开关式控制器
页数 文件大小 规格书
15页 302K
描述
High Speed PWM Controller

5962-8768102VEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.21Is Samacsys:N
其他特性:ALSO OPERATES IN CURRENT MODE模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:20 V最小输入电压:8.8 V
标称输入电压:12 VJESD-30 代码:R-GDIP-T16
长度:19.56 mm功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C最大输出电流:2.2 A
最大输出电压:5.15 V最小输出电压:5.05 V
标称输出电压:5.1 V封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.08 mm
子类别:Switching Regulator or Controllers表面贴装:NO
切换器配置:PUSH-PULL最大切换频率:1180 kHz
技术:BICMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:30k Rad(Si) V宽度:7.62 mm
Base Number Matches:1

5962-8768102VEA 数据手册

 浏览型号5962-8768102VEA的Datasheet PDF文件第2页浏览型号5962-8768102VEA的Datasheet PDF文件第3页浏览型号5962-8768102VEA的Datasheet PDF文件第4页浏览型号5962-8768102VEA的Datasheet PDF文件第5页浏览型号5962-8768102VEA的Datasheet PDF文件第6页浏览型号5962-8768102VEA的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢄ ꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢄ ꢃꢄ ꢅꢈ ꢇ  
ꢀꢁꢅ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢅ ꢃ ꢄ ꢅ ꢈꢇ ꢀ ꢁꢂ ꢃꢄ ꢉꢆ ꢇ  
www.ti.com  
SLUS334C − AUGUST 1995 − REVISED AUGUST 2004  
ꢐꢐ  
FEATURES  
DESCRIPTION  
D
D
D
Improved Versions of the UC3823/UC3825  
PWMs  
The UC3823A and UC3823B and the UC3825A and  
UC3825B family of PWM controllers are improved  
versions of the standard UC3823 and UC3825 family.  
Performance enhancements have been made to several  
of the circuit blocks. Error amplifier gain bandwidth product  
is 12 MHz, while input offset voltage is 2 mV. Current limit  
threshold is assured to a tolerance of 5%. Oscillator  
discharge current is specified at 10 mA for accurate dead  
time control. Frequency accuracy is improved to 6%.  
Startup supply current, typically 100 µA, is ideal for off-line  
applications. The output drivers are redesigned to actively  
sink current during UVLO at no expense to the startup  
current specification. In addition each output is capable of  
2-A peak currents during transitions.  
Compatible with Voltage-Mode or  
Current-Mode Control Methods  
Practical Operation at Switching Frequencies  
to 1 MHz  
D
50-ns Propagation Delay to Output  
D
High-Current Dual Totem Pole Outputs  
(2-A Peak)  
D
D
D
D
Trimmed Oscillator Discharge Current  
Low 100-µA Startup Current  
Pulse-by-Pulse Current Limiting Comparator  
Latched Overcurrent Comparator With Full  
Cycle Restart  
BLOCK DIAGRAM  
CLK/LEB 4  
(60%)  
13 VC  
RT  
CT  
5
6
7
3
2
1
11 OUTA  
*
OSC  
R
S
T
RAMP  
EAOUT  
NI  
D
1.25 V  
E/A  
14 OUTB  
12 PGND  
PWM  
LATCH  
PWM COMPARATOR  
9 mA  
INV  
SOFT−START COMPLETE  
RESTART  
CURRENT  
LIMIT  
5 V  
250mA  
DELAY  
LATCH  
SS  
8
1.0 V  
1.2 V  
0.2 V  
OVER CURRENT  
ILIM 9  
S
R
S
D
RESTART  
DELAY  
R
FAULT LATCH  
UVLO  
VCC 15  
GND 10  
”B” 16V/10V  
”A” 9.2V/8.4V  
INTERNAL  
BIAS  
VREF  
5.1 V  
ON/OFF  
4 V  
V
GOOD  
REF  
16 5.1 VREF  
UDG−02091  
* On the UC1823A version, toggles Q and Q are always low.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢏꢗ ꢔ ꢑꢀ ꢁ ꢖꢋ ꢔꢕ ꢑ ꢆꢖꢆ ꢙꢚ ꢛꢜ ꢝ ꢞꢟ ꢠꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠꢙ ꢜꢚ ꢨꢟ ꢠꢤꢩ ꢏꢝ ꢜꢨꢣ ꢢꢠꢡ  
ꢢ ꢜꢚ ꢛꢜꢝ ꢞ ꢠꢜ ꢡ ꢥꢤ ꢢ ꢙ ꢛꢙ ꢢ ꢟ ꢠꢙ ꢜꢚꢡ ꢥ ꢤꢝ ꢠꢪꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢖꢤꢫ ꢟꢡ ꢋꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ ꢡꢠ ꢟꢚꢨ ꢟꢝ ꢨ ꢬ ꢟꢝ ꢝ ꢟ ꢚꢠꢭꢩ  
ꢏꢝ ꢜ ꢨꢣꢢ ꢠ ꢙꢜ ꢚ ꢥꢝ ꢜ ꢢ ꢤ ꢡ ꢡ ꢙꢚ ꢮ ꢨꢜ ꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ ꢠꢤ ꢡꢠꢙ ꢚꢮ ꢜꢛ ꢟꢧ ꢧ ꢥꢟ ꢝ ꢟꢞ ꢤꢠꢤ ꢝ ꢡꢩ  
Copyright 2004, Texas Instruments Incorporated  

5962-8768102VEA 替代型号

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UC1825J TI

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