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5962-8768102VEA

更新时间： 2024-02-21 22:14:54
品牌 Logo 应用领域
德州仪器 - TI 稳压器开关式稳压器或控制器电源电路开关式控制器
页数 文件大小 规格书
15页 302K
描述
High Speed PWM Controller

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5962-8768102VEA 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N模拟集成电路 - 其他类型：SWITCHING CONTROLLER
控制模式：CURRENT-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：20 V最小输入电压：8.8 V
JESD-30 代码：S-CQCC-N20功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C最大输出电流：2.2 A
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装形状：SQUARE
封装形式：CHIP CARRIER认证状态：Not Qualified
表面贴装：YES切换器配置：PUSH-PULL
最大切换频率：1000 kHz技术：BIPOLAR
温度等级：MILITARY端子形式：NO LEAD
端子位置：QUADBase Number Matches：1

5962-8768102VEA 数据手册

 浏览型号5962-8768102VEA的Datasheet PDF文件第4页浏览型号5962-8768102VEA的Datasheet PDF文件第5页浏览型号5962-8768102VEA的Datasheet PDF文件第6页浏览型号5962-8768102VEA的Datasheet PDF文件第8页浏览型号5962-8768102VEA的Datasheet PDF文件第9页浏览型号5962-8768102VEA的Datasheet PDF文件第10页 
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ꢀꢁꢅ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢅ ꢃ ꢄ ꢅ ꢈꢇ ꢀ ꢁꢂ ꢃꢄ ꢉꢆ ꢇ  
www.ti.com  
ꢀꢁꢄ ꢃ ꢄ ꢉ ꢆꢇ ꢀꢁꢄ ꢃ ꢄ ꢉ ꢈꢇ ꢀꢁꢅ ꢃ ꢄ ꢉ ꢆꢇ ꢀ ꢁꢅ ꢃꢄ ꢉꢈ  
SLUS334C − AUGUST 1995 − REVISED AUGUST 2004  
LEADING EDGE BLANKING  
The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The  
UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less  
than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off.  
Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.  
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.  
On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM  
comparator, current limit comparator, or the overcurrent comparator.  
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse.  
Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the  
pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not  
require any filtering as result of leading edge blanking.  
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and  
the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy,  
an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%.  
The design equation is:  
ǒ Ǔ  
+ 0.5   R ø 10 kW   C  
t
LEB  
(2)  
Values of R less than 2 kΩ should not be used.  
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold,  
the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults  
without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this  
reason, some noise filtering may be required on the ILIM pin.  
UDG−95105  
Figure 4. Leading Edge Blanking Operational Waveforms  
7
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