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5962-8768101VEA PDF预览

5962-8768101VEA

更新时间: 2024-11-26 21:53:19
品牌 Logo 应用领域
德州仪器 - TI 开关控制器
页数 文件大小 规格书
17页 912K
描述
High Speed PWM Controller

5962-8768101VEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.14
Is Samacsys:N其他特性:CAN ALSO BE CONFIGURED IN CURRENT MODE
模拟集成电路 - 其他类型:SWITCHING CONTROLLER控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:30 V
最小输入电压:10 V标称输入电压:15 V
JESD-30 代码:R-GDIP-T16长度:19.56 mm
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
最大输出电流:2 A最大输出电压:5.15 V
最小输出电压:5.05 V标称输出电压:5.1 V
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Qualified筛选级别:MIL-PRF-38535 Class V
座面最大高度:5.08 mm子类别:Switching Regulator or Controllers
表面贴装:NO切换器配置:PUSH-PULL
最大切换频率:460 kHz技术:BIPOLAR
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:30k Rad(Si) V
宽度:7.62 mmBase Number Matches:1

5962-8768101VEA 数据手册

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application  
INFO  
UC1825  
UC2825  
UC3825  
available  
High Speed PWM Controller  
FEATURES  
DESCRIPTION  
Compatible with Voltage or Current Mode The UC1825 family of PWM control ICs is optimized for high fre-  
Topologies  
quency switched mode power supply applications. Particular care  
was given to minimizing propagation delays through the comparators  
and logic circuitry while maximizing bandwidth and slew rate of the  
error amplifier. This controller is designed for use in either cur-  
rent-mode or voltage mode systems with the capability for input volt-  
age feed-forward.  
Practical Operation Switching Frequencies  
to 1MHz  
50ns Propagation Delay to Output  
High Current Dual Totem Pole Outputs  
(1.5A Peak)  
Protection circuitry includes a current limit comparator with a 1V  
threshold, a TTL compatible shutdown port, and a soft start pin  
which will double as a maximum duty cycle clamp. The logic is fully  
latched to provide jitter free operation and prohibit multiple pulses at  
an output. An under-voltage lockout section with 800mV of hysteresis  
assures low start up current. During under-voltage lockout, the out-  
puts are high impedance.  
Wide Bandwidth Error Amplifier  
Fully Latched Logic with Double Pulse  
Suppression  
Pulse-by-Pulse Current Limiting  
Soft Start / Max. Duty Cycle Control  
Under-Voltage Lockout with Hysteresis  
Low Start Up Current (1.1mA)  
These devices feature totem pole outputs designed to source and  
sink high peak currents from capacitive loads, such as the gate of a  
power MOSFET. The on state is designed as a high level.  
BLOCK DIAGRAM  
UDG-92030-2  
SLUS235A - MARCH 1997 - REVISED MARCH 2004  

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