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5962-8685601RA PDF预览

5962-8685601RA

更新时间: 2024-11-26 05:05:35
品牌 Logo 应用领域
德州仪器 - TI 锁存器逻辑集成电路驱动
页数 文件大小 规格书
11页 345K
描述
OCTAL TRANSPARENT D-TYPE LATCHES

5962-8685601RA 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.29控制类型:ENABLE LOW/HIGH
计数方向:UNIDIRECTIONAL系列:HCT
JESD-30 代码:R-GDIP-T20JESD-609代码:e0
长度:24.195 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):0.16 mAProp。Delay @ Nom-Sup:60 ns
传播延迟(tpd):53 ns认证状态:Qualified
筛选级别:MIL-STD-883座面最大高度:5.08 mm
子类别:Bus Driver/Transceiver最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.62 mm

5962-8685601RA 数据手册

 浏览型号5962-8685601RA的Datasheet PDF文件第2页浏览型号5962-8685601RA的Datasheet PDF文件第3页浏览型号5962-8685601RA的Datasheet PDF文件第4页浏览型号5962-8685601RA的Datasheet PDF文件第5页浏览型号5962-8685601RA的Datasheet PDF文件第6页浏览型号5962-8685601RA的Datasheet PDF文件第7页 
ꢉ ꢀꢅꢊꢋ ꢅ ꢌꢊꢍꢎ ꢏꢊꢌꢐ ꢍꢅ ꢁꢑꢅ ꢒꢏ ꢐ ꢋꢊꢅꢀ ꢄ ꢐ  
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004  
CD54HCT573 . . . F PACKAGE  
CD74HCT573 . . . DB, E, OR M PACKAGE  
(TOP VIEW)  
D
D
4.5-V to 5.5-V V  
Operation  
CC  
Wide Operating Temperature Range of  
−55°C to 125°C  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
D
D
D
D
Balanced Propagation Delays and  
Transition Times  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
Standard Outputs Drive Up To 10 LS-TTL  
Loads  
Significant Power Reduction Compared to  
LS-TTL Logic ICs  
Inputs Are TTL-Voltage Compatible  
description/ordering information  
GND  
The ’HCT573 devices are octal transparent  
D-type latches. When the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is low, the Q outputs are latched at the  
logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
PDIP − E Tube  
CD74HCT573E  
CD74HCT573E  
HK573  
SSOP − DB Tape and reel  
Tube  
CD74HCT573DBR  
CD74HCT573M  
CD74HCT573M96  
CD54HCT573F3A  
−55°C to 125°C  
SOIC − M  
HCT573M  
Tape and reel  
CDIP − F  
Tube  
CD54HCT573F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢉ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢋꢑ ꢏꢌ ꢭ ꢑꢇꢮꢂ ꢇꢂꢈ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢉ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢈ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

5962-8685601RA 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT573E TI

完全替代

High Speed CMOS Logic Octal Transparent Latch, Three-State Output
CD54HCT573F3A TI

完全替代

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3 STATE OUTPUTS

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