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570BIT

更新时间: 2024-09-19 20:36:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 250K
描述
Clock Driver, 570 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8

570BIT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.07系列:570
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.175 ns座面最大高度:1.75 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm最小 fmax:170 MHz
Base Number Matches:1

570BIT 数据手册

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DATASHEET  
MULTIPLIER AND ZERO DELAY BUFFER  
ICS570  
Description  
Features  
The ICS570 is a high-performance Zero Delay Buffer (ZDB)  
which integrates IDT’s proprietary analog/digital Phase  
Locked Loop (PLL) techniques. The A version is  
8-pin SOIC package  
Available in Pb (lead) free package  
Pin-for-pin replacement and upgrade to ICS570M  
recommended for 5 V designs and the B version for  
Functional equivalent to AV9170 (not a pin-for-pin  
TM  
3.3 V designs. The chip is part of IDT’s ClockBlocks  
replacement)  
family, and was designed as a performance upgrade to  
meet today’s higher speed and lower voltage requirements.  
The zero delay feature means that the rising edge of the  
input clock aligns with the rising edges of both output  
clocks, giving the appearance of no delay through the  
device. There are two outputs on the chip, one being a  
low-skew divide by two of the other output. The device  
incorporates an all-chip power down/tri-state mode that  
stops the internal PLL and puts both outputs into a high  
impedance state.  
Low input to output skew of 300 ps max (>60 MHz  
outputs)  
Ability to choose between 14 different multipliers from  
0.5x to 32x  
Output clock frequency up to 170 MHz at 3.3 V  
Can recover degraded input clock duty cycle  
Output clock duty cycle of 45/55  
Power Down and Tri-State Mode  
Passes spread spectrum clock modulation  
Full CMOS clock swings with 25 mA drive capability at  
The ICS570 is ideal for synchronizing outputs in a large  
variety of systems, from personal computers to data  
communications to graphics/video. By allowing off-chip  
feedback paths, the device can eliminate the delay through  
other devices.  
TTL levels  
Advanced, low power CMOS process  
ICS570B has an operating voltage of 3.3 V (±5%)  
ICS570A has an operating voltage of 5.0 V (±5%)  
Industrial temperature version available  
The ICS570 A and B versions were designed to improve  
input to output jitter from the original ICS570M version, and  
are recommended for all new designs.  
Block Diagram  
ICLK  
S1:0  
Phase  
Detector,  
Charge  
Pum p,  
VCO  
CLK  
/2  
and Loop  
Filter  
CLK2  
divide  
by N  
FBIN  
External feedback can com e from CLK or CLK/2 (see table on page 2)  
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER  
1
ICS570  
REV K 073007  

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