Datasheet > 560BAC200M000BBG

560BAC200M000BBG

更新时间： 2024-09-17 09:38:35

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芯科 - SILICON		/
页数	文件大小	规格书
17页	925K
描述
LVDS Output Clock Oscillator,

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560BAC200M000BBG 数据手册

™

Ultra Series Crystal Oscillator

Si560 Data Sheet

Ultra Low Jitter Any-Frequency XO (90 fs), 0.2 to 3000 MHz

KEY FEATURES

The Si560 Ultra Series^™oscillator utilizes Silicon Laboratories’ advanced 4^thgenera-

tion DSPLL^®technology to provide an ultra-low jitter, low phase noise clock at any

output frequency. The device is factory-programmed to any frequency from 0.2 to

3000 MHz with <1 ppb resolution and maintains exceptionally low jitter for both inte-

ger and fractional frequencies across its operating range. The Si560 offers excellent

reliability and frequency stability as well as guaranteed aging performance. On-chip

power supply filtering provides industry-leading power supply noise rejection, simplify-

ing the task of generating low jitter clocks in noisy systems that use switched-mode

power supplies. Offered in industry-standard 3.2x5 mm and 5x7 mm footprints, the

Si560 has a dramatically simplified supply chain that enables Silicon Labs to ship cus-

tom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO,

where a different crystal is required for each output frequency, the Si560 uses one

simple crystal and a DSPLL IC-based approach to provide the desired output frequen-

cy. This process also guarantees 100% electrical testing of every device. The Si560 is

factory-configurable for a wide variety of user specifications, including frequency, out-

put format, and OE pin location/polarity. Specific configurations are factory-program-

med at time of shipment, eliminating the long lead times associated with custom oscil-

lators.

• Available with any frequency from 0.2

MHz to 3000 MHz

• Ultra low jitter: 90 fs RMS typical

(12 kHz – 20 MHz)

• Excellent PSRR and supply noise

immunity: –80 dBc Typ

• 20 ppm temp stability (–40 to 85 °C)

• 3.3 V, 2.5 V and 1.8 V V supply

operation from the same part number

• LVPECL, LVDS, CML, HCSL, CMOS,

and Dual CMOS output options

• 3.2x5, 5x7 mm package footprints

• Samples available with 1-2 week lead

times

APPLICATIONS

Pin Assignments

• 100G/200G/400G OTN, coherent optics

• 10G/40G/100G optical ethernet

• 56G/112G PAM4 clocking

VDD

CLK-

CLK+

OE/NC

NC/OE

GND

• 3G-SDI/12G-SDI/24G-SDI broadcast

video

• Datacenter

• Test and measurement

• FPGA/ASIC clocking

(Top View)

Fixed

Frequency

Crystal

Frequency

Flexible

DSPLL

Pin #

Descriptions

Low

Noise

Driver

1, 2

Selectable via ordering option

DCO

Digital

Phase

Detector

Digital

Phase Error

Loop

OE = Output enable; NC = No connect

OSC

Cancellation

Filter

Flexible

Formats,

1.8V – 3.3V

GND = Ground

Phase Error

Fractional

Operation

Divider

CLK+ = Clock output

NVM

Control

CLK- = Complementary clock output. Not used for CMOS.

VDD = Power supply

Power Supply Regulation

Output Enable

(Pin Control)

Built-in Power Supply

Noise Rejection

silabs.com | Building a more connected world.

Rev. 1.0

12 3 4 5 6 7...17

中文翻译

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