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54ACTQ646LM PDF预览

54ACTQ646LM

更新时间: 2024-11-11 17:04:11
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
9页 178K
描述
ACT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28, LCC-28

54ACTQ646LM 技术参数

生命周期:Obsolete包装说明:QCCN,
Reach Compliance Code:unknown风险等级:5.74
其他特性:WITH DIRECTION CONTROL系列:ACT
JESD-30 代码:S-CQCC-N28长度:11.43 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:1.905 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:2.54 mm
端子位置:QUAD宽度:11.43 mm
Base Number Matches:1

54ACTQ646LM 数据手册

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September 1998  
54ACTQ646  
Quiet Series Octal Transceiver/Register with 3-STATE  
Outputs  
General Description  
Features  
n Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
The ACTQ646 consist of registered bus transceiver circuits,  
with outputs, D-type flip-flops, and control circuitry providing  
multiplexed transmission of data directly from the input bus  
or from the internal storage registers. Data on the A or B bus  
will be loaded into the respective registers on the  
LOW-to-HIGH transition of the appropriate clock pin (CPAB  
or CPBA). The four fundamental handling functions available  
are illustrated in Figures 1, 2, 3, 4.  
n Independent registers for A and B busses  
n Multiplexed real-time and stored data transfers  
n 300 mil slim dual-in-line package  
n Outputs source/sink 24 mA  
n Faster prop delays than the standard AC/ACT646  
n 4 kV minimum ESD immunity  
The ACTQ utilizes FSC Quiet Series technology to guaran-  
tee quiet output switching and improved dynamic threshold  
n Standard Microcircuit Drawing (SMD) 5962-9219601  
performance. FACT Quiet Series features GTO output  
control and undershoot corrector in addition to a split ground  
bus for superior performance.  
Logic Symbols  
IEEE/IEC  
DS100326-1  
DS100326-2  
Pin Descriptions  
Pin Names  
Description  
A0–A7  
Data Register A Inputs  
Data Register A Outputs  
Data Register B Inputs  
Data Register B Outputs  
Clock Pulse Inputs  
B0–B7  
CPAB,  
CPBA  
SAB, SBA  
Transmit/Receive Inputs  
GTO is a trademark of National Semiconductor Corporation  
FACT and FACT Quiet Series are trademarks of Fairchild Semiconductor Corporation  
© 1998 National Semiconductor Corporation  
DS100326  
www.national.com  

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