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54ACTQ657SDMQR PDF预览

54ACTQ657SDMQR

更新时间: 2024-01-11 13:53:06
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
12页 216K
描述
ACT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CDIP24, 0.300 INCH, SLIM, CERAMIC, DIP-24

54ACTQ657SDMQR 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.74
系列:ACTJESD-30 代码:R-GDIP-T24
逻辑集成电路类型:BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:5.715 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

54ACTQ657SDMQR 数据手册

 浏览型号54ACTQ657SDMQR的Datasheet PDF文件第2页浏览型号54ACTQ657SDMQR的Datasheet PDF文件第3页浏览型号54ACTQ657SDMQR的Datasheet PDF文件第4页浏览型号54ACTQ657SDMQR的Datasheet PDF文件第5页浏览型号54ACTQ657SDMQR的Datasheet PDF文件第6页浏览型号54ACTQ657SDMQR的Datasheet PDF文件第7页 
March 1993  
74ACQ657 54ACTQ/74ACTQ657  
#
Quiet Series Octal Bidirectional Transceiver  
with 8-Bit Parity Generator/Checker  
and TRI-STATE Outputs  
É
General Description  
Features  
Y
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Combines the ’245 and the ’280 functions in one  
package  
The ’ACQ/’ACTQ657 contains eight non-inverting buffers  
with TRI-STATE outputs and an 8-bit parity generator/  
checker. Intended for bus oriented applications, the device  
combines the ’245 and the ’280 functions in one package.  
Y
Y
The ’ACQ/’ACTQ utilizes NSC Quiet Series technology to  
guarantee quiet output switching and improved dynamic  
threshold performance. FACT Quiet SeriesTM features  
GTOTM output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
Y
Y
Y
Y
300 mil 24-pin slim dual-in-line package  
Outputs source/sink 24 mA  
’ACTQ has TTL-compatible inputs  
Standard Military Drawing (SMD)  
Ð ’ACTQ657: 5962-92197  
Logic Symbols  
Connection Diagrams  
IEEE/IEC  
Pin Assignment  
for DIP, SOIC  
and Flatpak  
Pin Assignment  
for LCC  
TL/F/10636–3  
TL/F/10636–2  
TL/F/10636–1  
Pin Names  
Description  
A A  
0
Data Inputs/TRI-STATE Outputs  
Data Inputs/TRI-STATE Outputs  
Transmit/Receive Input  
Enable Input  
7
7
B B  
0
T/R  
OE  
PARITY  
Parity Input/TRI-STATE Output  
ODD/EVEN Parity Input  
Error TRI-STATE Output  
ODD/EVEN  
ERROR  
TL/F/10636–4  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10636  
RRD-B30M75/Printed in U. S. A.  

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